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公开(公告)号:US20220181499A1
公开(公告)日:2022-06-09
申请号:US17398550
申请日:2021-08-10
Applicant: SAMSUNG ELECTRONICS co., LTD.
Inventor: Su Jin Jung , Ki Hwan Kim , Sung Uk Jang , Young Dae Cho
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02 , H01L29/66
Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.
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公开(公告)号:US20220181459A1
公开(公告)日:2022-06-09
申请号:US17383022
申请日:2021-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young Dae Cho , Ki Hwan Kim , Sung Uk Jang , Su Jin Jung
IPC: H01L29/423 , H01L29/786 , H01L29/06 , H01L29/08
Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.
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公开(公告)号:US11257905B2
公开(公告)日:2022-02-22
申请号:US16386459
申请日:2019-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Uk Jang , Seung Hun Lee , Su Jin Jung , Young Dae Cho
IPC: H01L29/08 , H01L29/786 , H01L29/167 , H01L29/66 , H01L29/417 , H01L29/06 , H01L21/82 , H01L21/02 , H01L29/423
Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.
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14.
公开(公告)号:US10008600B2
公开(公告)日:2018-06-26
申请号:US15685459
申请日:2017-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Nam Kyu Kim , Dong Chan Suh , Kwan Heum Lee , Byeong Chan Lee , Cho Eun Lee , Su Jin Jung , Gyeom Kim , Ji Eon Yoon
IPC: H01L29/08 , H01L29/78 , H01L29/165 , H01L29/417
CPC classification number: H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/7834
Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
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