公开(公告)号：US11616076B2

公开(公告)日：2023-03-28

申请号：US17216867

申请日：2021-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US11610908B2

公开(公告)日：2023-03-21

申请号：US16833925

申请日：2020-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02

Abstract: A vertical memory device including: a substrate including a first and second regions; gate electrodes spaced apart from each other in a first direction, each of the gate electrodes extending in a second direction on the first and second regions, and the gate electrode are stacked on the second region; a channel extending in the first direction on the first region, the channel extending through the gate electrodes; a first conductive structure on an end portion of a first gate electrode, the end portion on the second region, the first gate electrode being disposed at a lowermost level; and a second conductive structure spaced apart from the first conductive structure in the second direction on the second region, the second conductive structure not overlapping the first gate electrode in the first direction and being disposed at a height different from that of the first conductive structure.

公开(公告)号：US11557603B2

公开(公告)日：2023-01-17

申请号：US17013724

申请日：2020-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158

Abstract: A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.

公开(公告)号：US20220231039A1

公开(公告)日：2022-07-21

申请号：US17685692

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US10811430B2

公开(公告)日：2020-10-20

申请号：US16272288

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Kwang-Soo Kim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/28

Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

公开(公告)号：US20190393238A1

公开(公告)日：2019-12-26

申请号：US16259086

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Geunwon LIM ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L23/522

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US09704878B2

公开(公告)日：2017-07-11

申请号：US15252931

申请日：2016-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

IPC: H01L21/70 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

公开(公告)号：US20250031364A1

公开(公告)日：2025-01-23

申请号：US18906403

申请日：2024-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US12137555B2

公开(公告)日：2024-11-05

申请号：US18348521

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US12027473B2

公开(公告)日：2024-07-02

申请号：US18227908

申请日：2023-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Kwon ,  Seokcheon Baek ,  Younghwan Son

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/562 ,  H01L23/528 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08146 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes first and second gate electrodes stacked and spaced apart from each other in a first direction on a first region of a substrate, and extending in staircase form in a second direction on a second region of the substrate, the second gate electrodes disposed on the first gate electrodes; a first support structure penetrating the first gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level lower than a level of a lowermost second gate electrode among the second gate electrodes; a second support structure penetrating at least one of the first and second gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level higher than a level of un uppermost second gate electrode among the second gate electrodes.