INTEGRATED CIRCUIT DEVICE
    11.
    发明申请

    公开(公告)号:US20220415782A1

    公开(公告)日:2022-12-29

    申请号:US17648598

    申请日:2022-01-21

    Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

    Mask layout correction method and a method for fabricating semiconductor devices using the same

    公开(公告)号:US11500283B2

    公开(公告)日:2022-11-15

    申请号:US16939828

    申请日:2020-07-27

    Abstract: Disclosed are mask layout correction methods and a method for fabricating semiconductor devices. The mask layout correction method comprises performing a first optical proximity correction on an initial pattern layout. The step of performing the first optical proximity correction includes providing a target pattern of the initial pattern layout with control points based on a first model, obtaining a predicted contour of the initial pattern layout by performing a simulation, and obtaining an error between the target pattern and the predicted contour from the control points. The control points include first control points on an edge of the target pattern and second control points in an inside of the target pattern. The step of obtaining the error includes acquiring first error values from the first control points, providing weights to the first error values, and acquiring second error values from the second control points.

    Manufacturing methods of semiconductor devices

    公开(公告)号:US11092885B2

    公开(公告)日:2021-08-17

    申请号:US16845459

    申请日:2020-04-10

    Abstract: A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.

    Method for fabricating mask by performing optical proximity correction

    公开(公告)号:US10031410B2

    公开(公告)日:2018-07-24

    申请号:US15334508

    申请日:2016-10-26

    Abstract: A mask fabricating method includes dividing an outline of a first design layout for a target layer into plural segments, selecting interest segments to be biased in a direction of approaching an outline of a second design layout for a lower layer of the target layer, performing optical proximity correction for the target layer based on a first cost function given to each of normal segments and a second cost function given to each of the interest segments, and fabricating the mask corresponding to the first design layout updated based on a result of the optical proximity correction. The second cost function includes a model of a margin between each of the interest segments and the outline of the second design layout. Performing the optical proximity correction includes biasing each of the interest segments up to a boundary defined by the margin.

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