公开(公告)号：US20170256305A1

公开(公告)日：2017-09-07

申请号：US15169590

申请日：2016-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Kyung-Chang Ryoo

IPC: G11C11/406 ,  G06F12/02 ,  G11C14/00

CPC classification number: G11C11/40618 ,  G06F12/023 ,  G06F2212/1044 ,  G06F2212/7211 ,  G11C7/24 ,  G11C14/00 ,  G11C16/3495 ,  G11C29/74

Abstract: A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be a randomized memory address; and periodically reassigning the randomized memory address to be a different memory address.

公开(公告)号：US12032828B2

公开(公告)日：2024-07-09

申请号：US17713228

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04 ,  G11C11/40611 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20230119291A1

公开(公告)日：2023-04-20

申请号：US18081488

申请日：2022-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0875 ,  G06F13/16 ,  G06F13/12

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

公开(公告)号：US11294571B2

公开(公告)日：2022-04-05

申请号：US16819032

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US11079936B2

公开(公告)日：2021-08-03

申请号：US15143248

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Prasun Gera ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F15/78 ,  G06F9/30

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

公开(公告)号：US11010242B2

公开(公告)日：2021-05-18

申请号：US16276369

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US10592114B2

公开(公告)日：2020-03-17

申请号：US15213386

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04 ,  G11C11/406 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US10558388B2

公开(公告)日：2020-02-11

申请号：US15169609

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Craig Hanson ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.

公开(公告)号：US10318434B2

公开(公告)日：2019-06-11

申请号：US15905746

申请日：2018-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F12/10 ,  G06F12/1018 ,  G06F12/0802 ,  G11C29/00 ,  G06F3/06

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

公开(公告)号：US10268541B2

公开(公告)日：2019-04-23

申请号：US15286460

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C29/42

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.