知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.019 seconds)

    Semiconductor memory device and a method of operating the semiconductor memory device
    12.
    发明授权
    Semiconductor memory device and a method of operating the semiconductor memory device 有权

    公开(公告)号：US11545211B2

    公开(公告)日：2023-01-03

    申请号：US17400585

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiheung Kim ,  Junhyung Kim ,  Sungchul Park ,  Hangyun Jung ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C11/4091 ,  G11C11/408 ,  G06F7/58 ,  G11C11/402

    Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    13.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12136463B2

    公开(公告)日：2024-11-05

    申请号：US18113702

    申请日：2023-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    VOLTAGE GENERATOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    16.
    发明公开
    VOLTAGE GENERATOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230216397A1

    公开(公告)日：2023-07-06

    申请号：US18063777

    申请日：2022-12-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGJU LEE ,  Kyungsoo Ha

    IPC: H02M3/07 ,  H02M1/00

    CPC classification number: H02M3/07 ,  H02M1/0025 ,  H02M1/0041 ,  G11C5/145

    Abstract: A voltage generator includes a charge pump circuit including a first charge pump having a plurality of first pumping capacitors, and a second charge pump having a plurality of second pumping capacitors having a capacitance different from a capacitance of each of the plurality of first pumping capacitors. The charge pump circuit is configured to supply a power supply voltage to a power mesh. The voltage generator further includes a controller configured to output a control signal based on a target level of the power supply voltage, and an oscillator configured to output a clock signal to the charge pump circuit. The oscillator outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    17.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11615861B2

    公开(公告)日：2023-03-28

    申请号：US17374822

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

Patent Agency Ranking