公开(公告)号：US12166097B2

公开(公告)日：2024-12-10

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US11888044B2

公开(公告)日：2024-01-30

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/82

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US09654118B2

公开(公告)日：2017-05-16

申请号：US15179202

申请日：2016-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan Bae ,  Kee-Won Kwon ,  Kyungho Kim ,  Jung Hoon Chun ,  Youngsoo Sohn ,  Seok Kim

IPC: H03L7/085 ,  H03D13/00 ,  H03L7/089 ,  H03L7/087 ,  H03L7/081 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

公开(公告)号：US20160089340A1

公开(公告)日：2016-03-31

申请号：US14866216

申请日：2015-09-25

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Sungchun Cho ,  Kyungho Kim ,  Euiseok Shin ,  Jongsun Kang ,  Jooho Shin ,  Juhyeon Bae ,  Hyeonju Jeong ,  Areum Jo ,  Sangchul Park

IPC: A61K31/045 ,  G01N33/50

Abstract: A method of increasing PGC-1α gene expression, decreasing PARIS gene expression, or promoting farnesylation of PARIS in a mammalian cell, the method comprising administering an effective amount of farnesol, a pharmaceutically acceptable salt thereof, or a solvate thereof to the cell; and related methods and compositions.

Abstract translation: 一种在哺乳动物细胞中增加PGC-1α基因表达，减少PARIS基因表达或促进PARIS的法呢基化的方法，该方法包括向细胞施用有效量的法呢醇，其药学上可接受的盐或其溶剂合物; 以及相关方法和组成。

公开(公告)号：US20230420535A1

公开(公告)日：2023-12-28

申请号：US18195074

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanghun Moon ,  Kyungho Kim ,  Kihwan Kim ,  Choeun Lee ,  Yonguk Jeon

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/41775 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/775

Abstract: A semiconductor device includes: an active region on a substrate extending in a first direction; a plurality of semiconductor layers spaced apart from each in a vertical direction on the active region, the plurality of semiconductor layers including lower and upper semiconductor layers; a gate structure on the substrate extending in a second direction to intersect the active region and the plurality of semiconductor layers; and a source/drain region on the active region and contacting the plurality of semiconductor layers. The source/drain region includes first epitaxial layers, including first layers on a side surface of the lower semiconductor layer and a second layer provided on and contacting the active region, and a second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction, and the first layer is between the second epitaxial layer and the side surface of the lower semiconductor layer.