公开(公告)号：US10651197B2

公开(公告)日：2020-05-12

申请号：US16192232

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Jun Hong ,  Ee Jou Kim ,  Joong Shik Shin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L29/792 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11529

Abstract: A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

公开(公告)号：US20220189876A1

公开(公告)日：2022-06-16

申请号：US17412408

申请日：2021-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Beyoung Hyun Koh ,  Yong Jin Kwon ,  Joong Shik Shin

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

公开(公告)号：US10680007B2

公开(公告)日：2020-06-09

申请号：US15933544

申请日：2018-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun Shin ,  Hyun Mog Park ,  Joong Shik Shin

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20190115366A1

公开(公告)日：2019-04-18

申请号：US16212240

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNG IL LEE ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

公开(公告)号：US10204919B2

公开(公告)日：2019-02-12

申请号：US15252740

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.