公开(公告)号：US11837645B2

公开(公告)日：2023-12-05

申请号：US18085871

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae Hwang ,  Wandon Kim ,  Geunwoo Kim ,  Heonbok Lee ,  Taegon Kim ,  Hanki Lee

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L21/285

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76886 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US11417656B2

公开(公告)日：2022-08-16

申请号：US16898719

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20220077295A1

公开(公告)日：2022-03-10

申请号：US17524259

申请日：2021-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Heonbok Lee ,  Chunghwan Shin ,  Youngsuk Chai ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.