公开(公告)号：US20190157444A1

公开(公告)日：2019-05-23

申请号：US16115114

申请日：2018-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gil Yang ,  Beom-Jin Park ,  Seung-Min Song ,  Geum-Jong Bae ,  Dong-Il Bae

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/308

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

公开(公告)号：US11894379B2

公开(公告)日：2024-02-06

申请号：US17844435

申请日：2022-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gil Yang ,  Geum-Jong Bae ,  Dong-Il Bae ,  Seung-Min Song ,  Woo-Seok Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/41 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/165 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/82385 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/7853 ,  H01L2924/13086

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

公开(公告)号：US10431585B2

公开(公告)日：2019-10-01

申请号：US15830981

申请日：2017-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gil Yang ,  Geum-Jong Bae ,  Dong-Il Bae ,  Seung-Min Song ,  Woo-Seok Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/41 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/165 ,  H01L29/20 ,  H01L29/78

Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode. The second source/drain region is connected to an edge of the second nanowire.

公开(公告)号：US10056454B2

公开(公告)日：2018-08-21

申请号：US15336111

申请日：2016-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Kim ,  Jong-Ho Lee ,  Geum-Jong Bae ,  Dong-Chan Suh

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/8234 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a semiconductor substrate. A first fin extends in a first direction. A first nano sheet structure includes at least two first nano sheets which extend in the first direction parallel to an upper surface of the first fin. A second fin extends in the first direction. A second nano sheet structure includes at least two second nano sheets which extend in the first direction parallel to an upper surface of the second fin. At least one of the at least two first nano sheets has a different thickness from at least one of the at least two second nano sheets.