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    SEMICONDUCTOR DEVICES
    11.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250048707A1

    公开(公告)日：2025-02-06

    申请号：US18604871

    申请日：2024-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Jinwoo BAE

    IPC: H01L29/66 ,  H01L23/528 ,  H10B12/00

    Abstract: A semiconductor device comprising: a substrate; a plurality of gate structures on the substrate, wherein the plurality of gate structures includes a first gate structure and a second gate structure that is adjacent the first gate structure; spacer structures on opposite sidewalls of the first gate structure; wherein the spacer structures comprise: insulating spacers on the opposite sidewalls of the first gate structure; an inner protective layer on the insulating spacers and an upper surface of the first gate structure; and an outer protective layer on at least a portion of the inner protective layer, an insulating filling layer on the spacer structures, wherein the insulating filling layer is between the first gate structure and the second gate structure; and an upper capping layer on an upper surface of the insulating filling layer, wherein the upper capping layer includes a same material as the insulating filling layer.

    CHEMICAL MECHANICAL POLISHING APPARATUS
    12.
    发明申请
    CHEMICAL MECHANICAL POLISHING APPARATUS 有权

    公开(公告)号：US20250033159A1

    公开(公告)日：2025-01-30

    申请号：US18662283

    申请日：2024-05-13

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： Seyun PARK ,  Donghoon KWON

    IPC: B24B37/20

    Abstract: A chemical mechanical polishing apparatus includes: a platen; a chemical mechanical polishing (CMP) pad on an upper surface of the platen, the CMP pad comprising an installation hole; a polishing head on the platen, the polishing head being configured to bring a wafer W into contact with the CMP pad; a slurry supply unit configured to supply slurry to the CMP pad; and a sensor module in the installation hole of the CMP pad, wherein the sensor module includes: a window at an upper end of the installation hole; a housing below the window, the housing comprising an inclined internal surface; and a sensor below the housing.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    15.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230389322A1

    公开(公告)日：2023-11-30

    申请号：US18133278

    申请日：2023-04-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongjin LEE ,  Junhee LIM ,  Donghoon KWON ,  Hakseon KIM ,  Nakjin SON ,  Yanghee LEE ,  Juhyun LEE

    IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    Abstract: A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    18.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240324172A1

    公开(公告)日：2024-09-26

    申请号：US18612672

    申请日：2024-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Yanghee Lee

    IPC: H10B12/00

    CPC classification number: H10B12/09 ,  H10B12/0335

    Abstract: A method of manufacturing a semiconductor device includes preparing a substrate including a plurality of active regions and a peripheral active region defined by an isolation layer, forming a word line in a word line trench that crosses the plurality of active regions, forming a plurality of bit line structures, each of the plurality of bit line structures including a bit line on the plurality of active regions, forming a plurality of gate line structures, each of the plurality of gate line structures including a gate line on the peripheral active region, forming a plurality of buried contacts between the plurality of bit line structures, the plurality of buried contacts being connected to the plurality of active regions, and forming an inter-gate insulating layer between the plurality of gate line structures, the inter-gate insulating layer including an oxide having impurities.

    WIRING STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    19.
    发明公开
    WIRING STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240194597A1

    公开(公告)日：2024-06-13

    申请号：US18527687

    申请日：2023-12-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Yanghee LEE ,  Jonghyuk PARK

    IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L28/90 ,  H10B12/315

    Abstract: A wiring structure includes a substrate; a lower insulating layer on the substrate; a lower wiring structure extending in a vertical direction and passing through the lower insulating layer; a spacer surrounding a side wall of the lower wiring structure; a capping insulating layer on the lower insulating layer; and a via structure extending in the vertical direction and passing through the capping insulating layer, wherein the via structure overlaps the lower wiring structure and the spacer in the vertical direction, and the via structure includes a protruding portion extending in the vertical direction and passing through at least a portion of the spacer.

    SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
    20.
    发明公开
    SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD 审中-公开

    公开(公告)号：US20240100647A1

    公开(公告)日：2024-03-28

    申请号：US18127382

    申请日：2023-03-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Boun YOON

    IPC: B24B37/20

    CPC classification number: B24B37/205

    Abstract: A substrate processing apparatus includes a substrate support portion including a platen and a transparent polishing pad on the platen, the platen comprising a light generator that generates light that passes through the transparent polishing pad and proceeds towards a semiconductor substrate on the substrate support portion, and the transparent polishing pad including a surface that contacts and polishes the semiconductor substrate. The substrate processing apparatus further includes: a substrate holder that fixes the semiconductor substrate such that the semiconductor substrate is in contact with the substrate support portion; and a slurry supply portion that supplies slurry between the semiconductor substrate and the transparent polishing pad. The slurry includes a light blocking material that blocks the light; and abrasive particles that are configured to be activated by accepting electrons generated, based on the light, by a photocatalyst within the slurry.

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