Abstract:
A data processing apparatus includes an electronic device configured to store data and instructions; a memory card; and a memory card socket in which the memory card is inserted. In certain disclosed systems and methods, the memory card socket includes: an insertion portion through which the memory card is inserted; a lock portion formed around an edge of the insertion portion, and that is configured to control attaching and detaching of the memory card based on instructions received from the electronic device; and a main body including the insertion portion and the lock portion and configured to accommodate the memory card via the insertion portion.
Abstract:
Disclosed is a biosensor. The biosensor comprises: an electrode; and a polymer structure disposed on the electrode and formed of poly-5,2′:5′,2″-terthiophene-3′-carboxylic acid (pTTCA), wherein an enzyme is present in a state of covalently binding with pTTCA inside the polymer structure.
Abstract:
An operation method of a UFS device including: determining, by a host, area information for write data, wherein in a turbo read the write data is stored in a non-pinned or pinned buffer area and in a normal read the write data is stored in a user storage; transferring, by the host, a first command UFS protocol information unit (UPIU); transferring, by the UFS device, an RTT UPIU to the host, transferring, by the host, a DATA OUT UPIU to the UFS device; mapping, by UFS device, a first logical block address with a physical address of an area corresponding to the area information; transferring, by the host, a second command UPIU; and performing the turbo read on the area to read data corresponding to the first logical block address when the area corresponding to the area information is the pinned or non-pinned turbo write buffer.
Abstract:
A memory system includes a host device including a host controller, and a memory device including a device controller and a non-volatile storage including a purge region and a memory region. The device controller communicates purge information associated with the purge region and including size information of the purge region. The host controller communicates a request for generating a first partition for a first logical unit in the memory region, and communicates a request for generating a second partition for a second logical unit in the purge region in response to the size information of the purge region.
Abstract:
A method includes transmitting a command signal including a time-out time from a host to a storage device; determining, by the storage device, a first time amount, which is an amount of time required for the storage device to perform an operation corresponding to the command signal; when the first time amount is not greater than the time-out time, providing a first response signal including a success flag from the storage device to the host after the storage device performs the operation within the time-out time; when the first time amount is longer than the time-out time, providing a second response signal including the first time amount and a time-out reset flag from the storage device to the host; and when the host receives the second response signal, retransmitting the command signal to the storage device after the host resets the time-out time to the first time amount.
Abstract:
An origin of a reference coordinate system is assigned to one of a plurality of center points, and center point coordinates according to the reference coordinate system are assigned to remaining center points, so that reference marks successively correspond to center points of a plurality of microscopes fixed to a base. Beam position detection marks disposed between the reference marks with exposure points of exposure heads fixed to the base are crossed to assign beam coordinates according to the reference coordinate system to the exposure points. Thus, alignment may be easily and accurately performed, and is effective for increasingly larger apparatuses.
Abstract:
A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.
Abstract:
A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.
Abstract:
A method for managing a replay protection memory block (RPMB) of a storage device includes allocating an RPMB master region managed separately from an RPMB region in which an RPMB key is stored in the RPMB of the storage device, programming a master key into the RPMB master region responsive to a request from a host, receiving a reset request for the RPMB region using the master key from the host, resetting the RPMB key in response to the reset request for the RPMB region, and receiving a reset lock request for the RPMB region from the host.
Abstract:
A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.