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    Semiconductor memory device and memory system including the same
    11.
    发明授权
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09064603B1

    公开(公告)日：2015-06-23

    申请号：US14185302

    申请日：2014-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Youn Youn ,  Su-A Kim ,  Hyo-Jin Choi ,  Chul-Woo Park ,  Hak-Soo Yu

    IPC: G11C7/10 ,  G11C11/409

    CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

    Abstract translation: 半导体存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括第一和第二子阵列，第一子阵列包括第一组阵列阵列，而第二子阵列包括第二组阵列阵列。 上部和下部排列阵列中的每一个包括相对于彼此具有不同定时参数的第一和第二部分。 控制逻辑控制对第一和第二部分的访问，使得在第一和第二部分上执行读/写操作。

    Refresh method, refresh address generator, volatile memory device including the same
    12.
    发明授权
    Refresh method, refresh address generator, volatile memory device including the same 有权
    刷新方法，刷新地址生成器，易失性存储器包括相同的

    公开(公告)号：US09042194B2

    公开(公告)日：2015-05-26

    申请号：US14057556

    申请日：2013-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

    IPC: G11C11/402 ,  G11C11/406 ,  G11C11/408 ,  G11C8/08 ,  G11C29/02

    CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/023 ,  G11C29/028 ,  G11C2211/4065

    Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

    Abstract translation: 用于易失性存储器件的刷新方法包括以具有第一刷新周期的第一刷新率来刷新阵列的第一组行的存储器单元，第一刷新率是具有比第二刷新率更长的刷新周期的较低速率 具有第二刷新周期，其中所述阵列的所述第一组行中的每个存储器单元具有比所述第一刷新周期更长的保持时间; 以及具有第三刷新周期的第三刷新率的阵列的第二组行的刷新存储单元，所述第三刷新率是具有比具有所述第二刷新周期的所述第二刷新率更短的刷新周期的较高速率，其中， 第二组行的每行的至少一个存储单元具有比第三刷新周期长的保留时间并且比第一刷新周期短。 第二刷新周期对应于在易失性存储器件的标准中定义的刷新周期。

    Electronic device for managing power and method of controlling same
    14.
    发明授权
    Electronic device for managing power and method of controlling same 有权

    公开(公告)号：US10545555B2

    公开(公告)日：2020-01-28

    申请号：US15261033

    申请日：2016-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yun-Hui Han ,  Min-Su Kim ,  Chul-Woo Park ,  Seung-Chul Choi

    IPC: G06F1/3206 ,  H02J7/00 ,  G05B15/02 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3203

    Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

    Memory device and memory system having the same
    16.
    发明授权
    Memory device and memory system having the same 有权

    公开(公告)号：US09685218B2

    公开(公告)日：2017-06-20

    申请号：US15236895

    申请日：2016-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Memory device and memory system having the same
    19.
    发明授权
    Memory device and memory system having the same 有权
    存储器件和存储器系统具有相同的功能

    公开(公告)号：US09536586B2

    公开(公告)日：2017-01-03

    申请号：US14514416

    申请日：2014-10-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Abstract translation: 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。

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