公开(公告)号：US09355703B2

公开(公告)日：2016-05-31

申请号：US14077187

申请日：2013-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Jin Lee ,  Dae-Hyun Kim ,  Sang-Yun Kim ,  Jae-Sung Kim ,  Young-Soo Sohn

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G11C29/028 ,  G11C29/50016

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract translation: 刷新地址生成器可以包括查找表，其包括存储与第一数据保留时间相关联的第一组地址的第一部分，以及存储与第二数据保留时间相关联的第二组地址的第二部分，该第二组地址与第一数据保留不同 时间，其中第一部分的地址比第二部分的地址更频繁地访问以刷新对应于地址的存储单元。 系统和方法也可以实现这种刷新地址生成。

公开(公告)号：US20240105255A1

公开(公告)日：2024-03-28

申请号：US18322894

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun Lee ,  Sang-Yun Kim ,  Jonghyuk Kim ,  Bok-Yeon Won

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

公开(公告)号：US10726886B2

公开(公告)日：2020-07-28

申请号：US16011662

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Yong Choi ,  Sang-Yun Kim ,  Soo-Bong Chang

IPC: G11C7/12 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

公开(公告)号：US10957379B2

公开(公告)日：2021-03-23

申请号：US16851744

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Hyun Lim ,  Sang-Yun Kim ,  Duk-Ha Park ,  Eun-Ah Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

公开(公告)号：US10665287B2

公开(公告)日：2020-05-26

申请号：US16027790

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Hyun Lim ,  Sang-Yun Kim ,  Duk-Ha Park ,  Eun-Ah Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

公开(公告)号：US11101695B2

公开(公告)日：2021-08-24

申请号：US15965274

申请日：2018-04-27

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Sung-Ku Yeo ,  Sang-Yun Kim ,  Jae-Seok Park ,  Young-Ho Ryu ,  Kang-Yoon Lee ,  Hamed Abbasizadeh ,  Sang-Wook Kwon ,  Thi Kim Nga Truong ,  Dong-In Kim ,  Sung-Bum Park ,  Dong-Soo Lee ,  Seung Il Huh

IPC: H02J7/00 ,  H02J7/14 ,  H02J50/12 ,  H02J50/70 ,  H02J7/02 ,  H02M7/217 ,  H02J50/20

Abstract: An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

公开(公告)号：US09653141B2

公开(公告)日：2017-05-16

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun Kim ,  Jong-Pil Son ,  Su-A Kim ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC: G06F12/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.