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公开(公告)号：US20180197485A1
公开(公告)日：2018-07-12
申请号：US15402136
申请日：2017-01-09
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany
IPC: G09G3/3291 , H01L27/092 , H01L29/78
CPC classification number: G09G3/3291 , G09G3/20 , G09G3/3614 , G09G2300/0426 , G09G2300/0828 , G09G2300/0871 , G09G2310/027 , G09G2310/0291 , H01L27/092 , H01L29/7816
Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.
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公开(公告)号：US12301347B2
公开(公告)日：2025-05-13
申请号：US17476387
申请日：2021-09-15
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Moonsang Hwang
IPC: H04L1/00 , H03K7/02 , H04L25/493 , H03M5/20 , H04N19/93
Abstract: A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.
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13.发明公开公开(公告)号：US20230268896A1
公开(公告)日：2023-08-24
申请号：US17725392
申请日：2022-04-20
Applicant: Samsung Display co,Ltd.
Inventor： Ali Fazli Yeknami , Anup P. Jose
CPC classification number: H03F3/45179 , H03F3/45475 , H04B1/0458 , H04B2001/0433
Abstract: An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA.
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公开(公告)号：US20230081418A1
公开(公告)日：2023-03-16
申请号：US17476387
申请日：2021-09-15
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Moonsang Hwang
IPC: H04L1/00
Abstract: A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.
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公开(公告)号：US11250780B2
公开(公告)日：2022-02-15
申请号：US16657680
申请日：2019-10-18
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Anup P. Jose , Gaurav Malhotra , Younghoon Song , Mohamed Elzeftawi
IPC: G09G3/3258 , G09G3/20
Abstract: A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.
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Patent Agency Ranking
公开(公告)号：US20210256897A1
公开(公告)日：2021-08-19
申请号：US16848706
申请日：2020-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Younghoon Song
IPC: G09G3/20
Abstract: A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.
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公开(公告)号：US11069282B2
公开(公告)日：2021-07-20
申请号：US16656423
申请日：2019-10-17
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Anup P. Jose , Gaurav Malhotra , Younghoon Song , Mohamed Elzeftawi
Abstract: A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.
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公开(公告)号：US20210049951A1
公开(公告)日：2021-02-18
申请号：US16656423
申请日：2019-10-17
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Anup P. Jose , Gaurav Malhotra , Younghoon Song , Mohamed Elzeftawi
Abstract: A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.
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公开(公告)号：US20210049943A1
公开(公告)日：2021-02-18
申请号：US16656447
申请日：2019-10-17
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohamed Elzeftawi
Abstract: A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.
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公开(公告)号：US20190280591A1
公开(公告)日：2019-09-12
申请号：US16109645
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon , Amir Amirkhany , Anup P. Jose
Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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