Abstract:
A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.
Abstract:
A display panel driving apparatus, including a gate driving part configured to output a gate signal to gate lines of a display panel, and a data driving part configured to output a data signal to a data line of the display panel, including a digital-analog converter, wherein the digital-analog converter is configured to convert a common voltage control data of digital format to a common voltage control voltage of analog format.
Abstract:
A display device includes a display panel including an edge extending along a first direction, a main circuit board adjacent to the edge of the display panel, and a connection circuit board which connects the main circuit board to the display panel at the edge thereof. The connection circuit board includes a plurality of board side pads which are arranged along the first direction and at which the connection circuit board is connected to the main circuit board. Each of the plurality of board side pads includes a first pad, and a second pad adjacent to the first pad along the first direction. The second pad includes a plurality of signal pads which are arranged along a second direction which crosses the first direction and are each aligned with the first pad along the first direction.
Abstract:
A display device includes a display panel, a main circuit board including a plurality of board pads arranged along a first direction, a connection circuit board electrically connected to the display panel and the main circuit board, and a driving chip disposed on the connection circuit board. The connection circuit board includes a plurality of board connection pads respectively connected to a plurality of board pads, a plurality of lines connecting the driving chip to the plurality of board connection pads to each other, and a test pattern disposed spaced part from the driving chip, where a first line and a second line among the lines are electrically connected to the test pattern, and a same voltage is applied to the first line and the second line.
Abstract:
A display device includes a display panel including an edge extending along a first direction, a main circuit board adjacent to the edge of the display panel, and a connection circuit board which connects the main circuit board to the display panel at the edge thereof. The connection circuit board includes a plurality of board side pads which are arranged along the first direction and at which the connection circuit board is connected to the main circuit board. Each of the plurality of board side pads includes a first pad, and a second pad adjacent to the first pad along the first direction. The second pad includes a plurality of signal pads which are arranged along a second direction which crosses the first direction and are each aligned with the first pad along the first direction.
Abstract:
A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.
Abstract:
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
Abstract:
A display device includes: a display panel including first pads arranged along a first direction, and second pads spaced apart from the first pads; a first connection circuit board electrically connected to the first pads; and a second connection circuit board electrically connected to the second pads. The first connection circuit board includes: first output pads electrically connected to the first pads; and at least two first protrusion parts spaced along the first direction and protruding in a second direction crossing the first direction. The second connection circuit board includes: second output pads electrically connected to the second pads; and at least one second protrusion part protruding in the second direction, and located between the first protrusion parts when viewed on a plane that is parallel to a surface of the display panel.
Abstract:
A data driver includes a plurality of amplifiers configured to output a plurality of data voltages to a plurality of data lines. The amplifiers are configured to output the data voltages to the corresponding data lines in a writing mode. Only one of the plurality of amplifiers is configured to output a sensing data voltage to the plurality of data lines in a sensing mode.
Abstract:
A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.