公开(公告)号：US20220352147A1

公开(公告)日：2022-11-03

申请号：US17863137

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric GAY ,  Abderrezak MARZAKI

IPC: H01L27/06 ,  H01L21/8249 ,  H01L29/732

Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

公开(公告)号：US20220344327A1

公开(公告)日：2022-10-27

申请号：US17723706

申请日：2022-04-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.

公开(公告)号：US20220157931A1

公开(公告)日：2022-05-19

申请号：US17591233

申请日：2022-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L49/02 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

公开(公告)号：US20210313280A1

公开(公告)日：2021-10-07

申请号：US17351930

申请日：2021-06-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Mathieu LISART

IPC: H01L23/00 ,  G06F21/87 ,  H04N19/44 ,  H01L27/02 ,  G06F21/75

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

公开(公告)号：US20210288189A1

公开(公告)日：2021-09-16

申请号：US17196226

申请日：2021-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L29/94 ,  H01L27/11531 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

公开(公告)号：US20210167062A1

公开(公告)日：2021-06-03

申请号：US17108830

申请日：2020-12-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric GAY ,  Abderrezak MARZAKI

IPC: H01L27/06 ,  H01L21/8249

Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

公开(公告)号：US20190067291A1

公开(公告)日：2019-02-28

申请号：US16111480

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20190067274A1

公开(公告)日：2019-02-28

申请号：US16111716

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/306 ,  H01L21/283 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11521

Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.

公开(公告)号：US20240074134A1

公开(公告)日：2024-02-29

申请号：US18230952

申请日：2023-08-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Paul DEVOGE ,  Abderrezak MARZAKI ,  Franck JULIEN ,  Alexandre MALHERBE

IPC: H10B10/00 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B10/12 ,  H01L29/66825 ,  H01L29/788

Abstract: An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.

公开(公告)号：US20240030357A1

公开(公告)日：2024-01-25

申请号：US18224293

申请日：2023-07-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/8725 ,  H01L29/66143 ,  H01L29/0619

Abstract: A semiconductor device includes a Schottky diode on a substrate. The Schottky diode includes a layer of polysilicon disposed on a dielectric layer within the substrate that is configured to electrically insulate the layer of polysilicon from the substrate. The layer of polysilicon includes an N-type doped first cathode region adjacent to an undoped second anode region. A first metal contact is disposed on a surface of the N-type doped first cathode region and a second metal contact is disposed on a surface of the undoped second anode region. The first metal contact and second metal contact are electrically insulated from each other by an insulating layer on the layer of polysilicon.