公开(公告)号：US10826334B2

公开(公告)日：2020-11-03

申请号：US15940551

申请日：2018-03-29

Applicant: Silicon Laboratories Inc.

Inventor： Krishna Pentakota ,  Huanhui Zhan

IPC: H02M3/335 ,  H02J50/70 ,  H01L23/495 ,  H03B5/12 ,  H02J50/12

Abstract: A power transfer device includes an oscillator circuit of a DC/AC power converter responsive to an input DC signal and an oscillator enable signal to generate an AC signal. The oscillator circuit includes a first node, a second node, and a circuit coupled between the first node and the second node. The circuit includes a cross-coupled pair of devices. The oscillator circuit further includes a variable capacitor coupled between the first node and the second node. A capacitance of the variable capacitor is based on a digital control signal. A first frequency of a pseudo-differential signal on the first node and the second node is based on the capacitance. The power transfer device further includes a control circuit configured to periodically update the digital control signal. A second frequency of periodic updates to the digital control signal is different from the first frequency.

公开(公告)号：US10511273B2

公开(公告)日：2019-12-17

申请号：US15835230

申请日：2017-12-07

Applicant: Silicon Laboratories Inc.

Inventor： Mohammad Al-Shyoukh ,  Krishna Pentakota ,  Stefan N. Mastovich

IPC: H03F3/217 ,  H02J50/05 ,  H02J50/80 ,  H02M3/335 ,  H02M5/458 ,  H02M7/797 ,  H02M1/08 ,  H01L29/66 ,  H02M3/338 ,  H02M1/34 ,  H02H9/00 ,  H03F3/04 ,  H01L29/78 ,  H02M1/00 ,  H02M1/32

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

公开(公告)号：US20190305608A1

公开(公告)日：2019-10-03

申请号：US15940551

申请日：2018-03-29

Applicant: Silicon Laboratories Inc.

Inventor： Krishna Pentakota ,  Huanhui Zhan

IPC: H02J50/70 ,  H01L23/495 ,  H02M3/335 ,  H02J50/12 ,  H03B5/12

Abstract: A power transfer device includes an oscillator circuit of a DC/AC power converter responsive to an input DC signal and an oscillator enable signal to generate an AC signal. The oscillator circuit includes a first node, a second node, and a circuit coupled between the first node and the second node. The circuit includes a cross-coupled pair of devices. The oscillator circuit further includes a variable capacitor coupled between the first node and the second node. A capacitance of the variable capacitor is based on a digital control signal. A first frequency of a pseudo-differential signal on the first node and the second node is based on the capacitance. The power transfer device further includes a control circuit configured to periodically update the digital control signal. A second frequency of periodic updates to the digital control signal is different from the first frequency.

公开(公告)号：US20190181817A1

公开(公告)日：2019-06-13

申请号：US15835230

申请日：2017-12-07

Applicant: Silicon Laboratories Inc.

Inventor： Mohammad Al-Shyoukh ,  Krishna Pentakota ,  Stefan N. Mastovich

IPC: H03F3/217 ,  H02J50/05 ,  H02J50/80 ,  H02M3/335 ,  H02M5/458 ,  H02M7/797 ,  H01L29/66 ,  H02M1/08

CPC classification number: H03F3/217 ,  H01L29/66106 ,  H01L29/66143 ,  H01L29/7816 ,  H02H9/005 ,  H02J50/05 ,  H02J50/80 ,  H02M1/08 ,  H02M1/32 ,  H02M1/34 ,  H02M3/33515 ,  H02M3/33592 ,  H02M3/3387 ,  H02M5/458 ,  H02M7/797 ,  H02M2001/0003 ,  H03F3/04 ,  H03F3/2171

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

公开(公告)号：US09231579B2

公开(公告)日：2016-01-05

申请号：US14074241

申请日：2013-11-07

Applicant: SILICON LABORATORIES INC.

Inventor： Ruifeng Sun ,  Mustafa H. Koroglu ,  Ramin Khoini Poorfard ,  Yu Su ,  Krishna Pentakota ,  Pio Balmelli

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/16

CPC classification number: H03K17/16 ,  H03K2217/0063

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。

公开(公告)号：US10566930B2

公开(公告)日：2020-02-18

申请号：US15498937

申请日：2017-04-27

Applicant: Silicon Laboratories Inc.

Inventor： Krishna Pentakota ,  Aslamali Rafi

IPC: H03L5/00 ,  H03B5/12 ,  H03F3/19

Abstract: In one embodiment, an apparatus includes a voltage controlled oscillator (VCO) to output an oscillating signal. The VCO may have a tank formed of at least one capacitor coupled in parallel with at least one inductor, and a plurality of transconductors to provide energy to the tank. At least one of the plurality of transconductors can be controllably switched to be coupled to the tank or to be decoupled from the tank.

公开(公告)号：US20150123714A1

公开(公告)日：2015-05-07

申请号：US14074241

申请日：2013-11-07

Applicant: SILICON LABORATORIES INC.

Inventor： Ruifeng Sun ,  Mustafa H. Koroglu ,  Ramin Khoini Poorfard ,  Yu Su ,  Krishna Pentakota ,  Pio Balmelli

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03K2217/0063

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。