公开(公告)号：US12218100B2

公开(公告)日：2025-02-04

申请号：US17680617

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyo Hwang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.

公开(公告)号：US12033948B2

公开(公告)日：2024-07-09

申请号：US17539963

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US12002786B2

公开(公告)日：2024-06-04

申请号：US17535904

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/81815

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.

公开(公告)号：US20240079336A1

公开(公告)日：2024-03-07

申请号：US18236190

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun CHUNG ,  Young Lyong Kim ,  In Hyo Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253

Abstract: Provided is a semiconductor package. The semiconductor package includes a redistribution line structure comprising a plurality of redistribution line patterns; a first semiconductor chip and a second semiconductor chip on the redistribution line structure and spaced apart from each other; a bridge structure between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and comprising a plurality of connection wiring patterns configured to electrically connect the first semiconductor chip to the second semiconductor chip; and a molding layer surrounding a sidewall of the bridge structure and filled between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and between the first semiconductor chip and the second semiconductor chip, wherein lowermost surfaces of the plurality of connection wiring patterns are above uppermost surfaces of the plurality of redistribution line patterns.

公开(公告)号：US11462479B2

公开(公告)日：2022-10-04

申请号：US16548813

申请日：2019-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geol Nam ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.

公开(公告)号：US12100681B2

公开(公告)日：2024-09-24

申请号：US18491551

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0807 ,  H01L2224/0903 ,  H01L2224/13111 ,  H01L2224/16013 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

公开(公告)号：US20240290756A1

公开(公告)日：2024-08-29

申请号：US18655932

申请日：2024-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/81815

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.

公开(公告)号：US20240047402A1

公开(公告)日：2024-02-08

申请号：US18491551

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/81 ,  H01L24/13 ,  H01L24/17 ,  H01L24/05 ,  H01L24/09 ,  H01L24/08 ,  H01L25/105 ,  H01L2224/0807 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/16013 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/13111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/1703 ,  H01L2224/0903

Abstract: A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

公开(公告)号：US11817411B2

公开(公告)日：2023-11-14

申请号：US17366145

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0807 ,  H01L2224/0903 ,  H01L2224/13111 ,  H01L2224/16013 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

公开(公告)号：US10964670B2

公开(公告)日：2021-03-30

申请号：US16225074

申请日：2018-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeong Kim ,  Young Lyong Kim ,  Geol Nam

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.