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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210305153A1

    公开(公告)日：2021-09-30

    申请号：US17153963

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

    SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP
    13.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP 有权

    公开(公告)号：US20210043591A1

    公开(公告)日：2021-02-11

    申请号：US16795658

    申请日：2020-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

    IPC: H01L23/00 ,  H01L21/56

    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

    SEMICONDUCTOR DEVICES
    18.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230077803A1

    公开(公告)日：2023-03-16

    申请号：US17751740

    申请日：2022-05-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

    SEMICONDUCTOR DEVICES INCLUDING SCRIBE LANE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICES
    20.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SCRIBE LANE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220223485A1

    公开(公告)日：2022-07-14

    申请号：US17706401

    申请日：2022-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung CHOI ,  Junyong NOH ,  Yeonjin LEE ,  Junghoon HAN

    IPC: H01L21/66 ,  H01L21/78

    Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

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