公开(公告)号：US20220278201A1

公开(公告)日：2022-09-01

申请号：US17749719

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Kyengmun KANG ,  Juyon SUH ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

公开(公告)号：US20210057445A1

公开(公告)日：2021-02-25

申请号：US16910199

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil KIM ,  Sungjin KIM ,  Seulye KIM ,  Junghwan KIM ,  Chanhyoung KIM

IPC: H01L27/11582 ,  H01L29/10

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

公开(公告)号：US20200243558A1

公开(公告)日：2020-07-30

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20220384482A1

公开(公告)日：2022-12-01

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  Dongkyum KIM ,  Seulye KIM ,  Ji-Hoon CHOI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/04 ,  H01L29/423 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US20220115294A1

公开(公告)日：2022-04-14

申请号：US17331951

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil KIM ,  Jinhyuk KIM ,  Jung-Hwan KIM

IPC: H01L23/48 ,  H01L29/78 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

公开(公告)号：US20210043647A1

公开(公告)日：2021-02-11

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  Dongkyum KIM ,  Seulye KIM ,  Ji-Hoon CHOI

IPC: H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.