公开(公告)号：US20190181226A1

公开(公告)日：2019-06-13

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Dongkyum KIM ,  Sunggil KIM ,  Seulye KIM ,  Sangsoo LEE ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US20210313427A1

公开(公告)日：2021-10-07

申请号：US17085467

申请日：2020-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Kyengmun KANG ,  Juyon SUH ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

公开(公告)号：US20220278201A1

公开(公告)日：2022-09-01

申请号：US17749719

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Kyengmun KANG ,  Juyon SUH ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.