公开(公告)号：US11728343B2

公开(公告)日：2023-08-15

申请号：US17506785

申请日：2021-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Soonmoon Jung

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/18 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/187 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/1608 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

公开(公告)号：US11588054B2

公开(公告)日：2023-02-21

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.