公开(公告)号：US20170207137A1

公开(公告)日：2017-07-20

申请号：US14997823

申请日：2016-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng DING ,  Junjung KIM ,  Jeong Hoon AHN

IPC: H01L21/66 ,  H01L21/78 ,  H01L23/544 ,  G01R31/28 ,  G01R31/26

CPC classification number: H01L22/32 ,  G01R31/2644 ,  G01R31/2884 ,  H01L21/78 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5446

Abstract: A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.

公开(公告)号：US20230170289A1

公开(公告)日：2023-06-01

申请号：US17811342

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Seong JANG ,  Won Ji PARK ,  Jeong Hoon AHN ,  Jae Hee OH ,  Ji Hyung KIM ,  Shaofeng DING ,  Seok Jun HONG ,  Je Gwan HWANG

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/64 ,  H01L23/538 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01L23/642 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/0655 ,  H01L28/91 ,  H01L24/16 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/37001

Abstract: An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.

公开(公告)号：US20230131382A1

公开(公告)日：2023-04-27

申请号：US17843594

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng DING ,  Jihyung KIM ,  Won Ji PARK ,  Jeong Hoon AHN ,  Jaehee OH ,  Yun Ki CHOI

IPC: H01L27/06 ,  H01L25/07 ,  H01L27/02

Abstract: Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer. The passive device die includes: a second substrate including a front side and a back side that are opposite to each other, the front side of the second substrate facing the front side of the first substrate; an interlayer dielectric layer on the front side of the second substrate, the interlayer dielectric layer including at least one hole; a passive device in the hole; and a second wiring layer on the passive device, wherein the second wiring layer faces and is connected to the first wiring layer.

公开(公告)号：US20220271045A1

公开(公告)日：2022-08-25

申请号：US17474436

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC: H01L27/11 ,  H01L27/108 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

公开(公告)号：US20210242203A1

公开(公告)日：2021-08-05

申请号：US17034296

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng DING ,  Minguk KANG ,  Jihyung KIM ,  Jeong Hoon AHN ,  Haeri YOO ,  Yun Ki CHOI

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L25/065

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.

公开(公告)号：US20210118794A1

公开(公告)日：2021-04-22

申请号：US16881452

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng DING ,  Jae June JANG ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L49/02

Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

公开(公告)号：US20200006199A1

公开(公告)日：2020-01-02

申请号：US16239726

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng DING ,  So Ra Park ,  Jeong Hoon Ahn

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.