公开(公告)号：US20220093144A1

公开(公告)日：2022-03-24

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  KYUNG-SOO HA ,  YOUNG-SOO SOHN ,  KI-SEOK OH ,  CHANG-KYO LEE ,  JIN-HOON JANG ,  YEON-KYU CHOI ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20190259429A1

公开(公告)日：2019-08-22

申请号：US16103261

申请日：2018-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-SEOK HEO ,  JOUNG-WOOK MOON ,  KI-HO KIM ,  JIN-HYEOK BAEK ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/14 ,  G11C11/413 ,  G11C11/4074 ,  G11C16/28 ,  G06F1/26

Abstract: A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.