公开(公告)号：US20230197450A1

公开(公告)日：2023-06-22

申请号：US17931150

申请日：2022-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn

IPC: H01L21/033 ,  H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L27/10876 ,  H01L27/10897 ,  H01L21/76229 ,  H01L21/3086 ,  H01L21/0332 ,  H01L21/3081

Abstract: A semiconductor device fabrication method includes forming a substrate having first and second regions therein, with different densities of active regions in the first and second regions. A cell trench is formed, which defines cell active regions in the first region, and a peripheral trench is formed, which defines peripheral active regions in the second region. A first insulating layer is formed in the cell trench and the peripheral trench. A mask is selectively formed, which covers the first insulating layer in the first region and exposes the first insulating layer in the second region. A second insulating layer is formed on the first insulating layer in the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process. The first insulating layer is exposed in the first region by removing the mask. A third insulating layer is formed on the first insulating layer in the first region and on the second insulating layer in the second region.

公开(公告)号：US20240196596A1

公开(公告)日：2024-06-13

申请号：US18350863

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device may include an active pattern on a substrate and at least partially surrounded by a device isolation pattern, a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode including lower and upper portions, and a side-capping pattern on a top surface of the lower portion of the gate electrode. The side-capping pattern may be on a side surface of the upper portion of the gate electrode, and a top surface of the side-capping pattern may be located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.

公开(公告)号：US20240032286A1

公开(公告)日：2024-01-25

申请号：US18335186

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chansic Yoon ,  Jongmin Kim ,  Kiseok Lee ,  Junhyeok Ahn

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/485 ,  H10B12/482 ,  H01L29/42356

Abstract: Provided is an integrated circuit device including a substrate that includes an active region defined by a trench isolation, a word line that extends in a first horizontal direction inside the substrate across the active region, a bit line that extends on the word line in a second horizontal direction orthogonal to the first horizontal direction, a direct contact that electrically connects the bit line to the active region, a pad that is on the active region and has a horizontal width that is greater than that of the active region, a buried contact that contacts a sidewall of the pad, and a conductive landing pad that extends on the buried contact in a vertical direction and faces the bit line in the first horizontal direction.

公开(公告)号：US20240023318A1

公开(公告)日：2024-01-18

申请号：US18319601

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/488 ,  H10B12/485 ,  H10B12/03

Abstract: A semiconductor device includes an active region between portions of a device isolation layer on a substrate, a self-aligned pad layer on a first region of the active region, a bit line that is electrically connected to a second region of the active region, and a contact structure on a side surface of the bit line and electrically connected to the self-aligned pad layer. The self-aligned pad layer includes a pad protrusion that extends along an upper portion of a side surface of the first region of the active region, and a side of the self-aligned pad layer is in contact with the device isolation layer.

公开(公告)号：US11688779B2

公开(公告)日：2023-06-27

申请号：US17387427

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Junhyeok Ahn ,  Jae Hyun Yoon ,  Myeong-Dong Lee ,  Seok Hwan Lee ,  Sunghee Han ,  Inkyoung Heo

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/45 ,  H01L27/108

CPC classification number: H01L29/41775 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1606 ,  H01L27/10814 ,  H01L29/45

Abstract: A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

公开(公告)号：US20230145857A1

公开(公告)日：2023-05-11

申请号：US17935119

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYERAN LEE ,  Sohyun Park ,  Junhyeok Ahn

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063

Abstract: A semiconductor device includes a conductive contact plug disposed on a substrate, a bit line structure disposed on the conductive contact plug, first and second spacers, and a capping pattern disposed on the first and second spacers. The conductive contact plug includes a lower portion that has a first width and an upper portion that has a second width narrower than the first width. The bit line structure includes a conductive structure and an insulation structure stacked in a vertical direction. The first and second spacers are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction. The capping pattern covers a sidewall of the upper portion of the conductive contact plug. The first spacer directly contacts the sidewall of the lower portion of the conductive contact plug and includes air.