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    INTEGRATED CIRCUIT DEVICE
    11.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240321726A1

    公开(公告)日：2024-09-26

    申请号：US18419715

    申请日：2024-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo LEE ,  Yubo QIAN ,  Hyunjae KANG ,  Gyeongseop KIM ,  Sutae KIM ,  Jaeyoung PARK ,  Jeonwon JEONG

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

    CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L27/0886

    Abstract: An integrated circuit device includes a first conductive pattern disposed on a substrate, a second conductive pattern surrounding a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulation structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern penetrating through the upper insulation structure and extending in a vertical direction, wherein the upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension extending from a portion of the main plug portion toward the substrate, covering an upper of the upper sidewall of the first conductive pattern, and overlapping the second conductive pattern in the vertical direction, and a dummy contact is formed on a single diffusion break region on the substrate.

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250048723A1

    公开(公告)日：2025-02-06

    申请号：US18645844

    申请日：2024-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo LEE ,  Sutae KIM

    IPC: H01L27/088 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate having first and second surfaces; an active pattern extending on the first surface of the substrate, the active pattern having first and second conductivity-type impurity regions, the first and second conductivity-type impurity regions in contact with each other; semiconductor patterns stacked on a portion of the active pattern between the first and second conductivity-type impurity regions; an inactive gate structure extending across the portion of the active pattern between the first and second conductivity-type impurity regions, the inactive gate structure surrounding the semiconductor patterns; a first contact passing through the substrate from the second surface of the substrate and connected to the first conductivity-type impurity region; and a second contact passing through the substrate from the second surface of the substrate and connected to the second conductivity-type impurity region.

    METHOD OF INSPECTING DEFECTS
    18.
    发明申请
    METHOD OF INSPECTING DEFECTS 有权

    公开(公告)号：US20250014169A1

    公开(公告)日：2025-01-09

    申请号：US18644638

    申请日：2024-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bumjoo LEE ,  Jinwoo LEE ,  Suyoung LEE

    IPC: G06T7/00 ,  G06T5/20 ,  G06T5/70 ,  G06T7/11

    Abstract: A defect inspection method includes: recognizing image peaks that are reference positions of image patterns included an inspection image; performing filtering on a reference image including reference patterns, recognizing reference peaks, and then selecting some of the reference peaks as peak samples; calculating candidate correction constants by overlapping the filtered inspection image and the filtered reference image, and then selecting a primary correction constant among the candidate correction constants; applying the first correction constant to the reference image and selecting a secondary correction constant by matching the image peaks to the reference peaks included in a primary corrected reference image, and then applying the secondary correction constant to the primary corrected reference image and forming a secondary corrected reference image aligned with the inspection image; and performing a defect inspection on the inspection image by matching the image patterns to reference patterns included in the secondary corrected reference image.

    VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME
    19.
    发明公开
    VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240196763A1

    公开(公告)日：2024-06-13

    申请号：US18214755

    申请日：2023-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN ,  Jooheon KANG ,  Jinwoo LEE

    IPC: H10N70/00 ,  H10B63/00

    CPC classification number: H10N70/826 ,  H10B63/84 ,  H10N70/8833

    Abstract: A variable resistance memory device includes a pillar, a resistance change layer provided at a side surface of the pillar, a semiconductor layer provided at a side surface of the resistance change layer, a gate insulating layer provided at a side surface of the semiconductor layer, a plurality of isolating layers and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer, and an internal resistance layer between the resistance change layer and the semiconductor layer, where a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer includes conductor characteristics and the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer includes insulator characteristics.

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