公开(公告)号：US09530838B2

公开(公告)日：2016-12-27

申请号：US14826075

申请日：2015-08-13

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Akio Ichimura ,  Toshiaki Igarashi ,  Yasuhiro Shirai

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L29/045 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7827

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract translation: 改善半导体器件（垂直功率MOSFET）的特性。 在围绕形成有半导体元件的单元区域的周边区域中形成具有角部的螺旋状p型列区域。 在围绕形成有半导体元件的单元区域的外围区域的外延层中，形成螺旋状包围单元区域并且具有构成拐角的第一和第二侧面的沟槽，并且沟槽被外延层填充 。 通过以这种方式螺旋地布置p型列区域（n型列区域），可以避免由于热点导致的耐受电压裕度的下降。 此外，保持p型列区域（n型列区域）的连续性。 结果，电场浓度逐渐减小到外周，耐压提高。

公开(公告)号：US08647948B2

公开(公告)日：2014-02-11

申请号：US13742489

申请日：2013-01-16

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yuya Abiko ,  Junichi Kogure

IPC: H01L21/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.