公开(公告)号：US20160013179A1

公开(公告)日：2016-01-14

申请号：US14752880

申请日：2015-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinao MIURA

IPC: H01L27/06 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0605 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Reduction of the speed of switching between the drain electrodes of transistors and the cathode electrodes of diodes due to the inductances of lines coupling them is inhibited. Transistors and diodes are formed over a substrate. The transistors and the diodes are arranged in a first direction. The substrate also includes a first line, first branch lines, and second branch lines formed thereover. The first line extends between the transistors and the diodes. The first branch lines are formed to branch from the first line in a direction to overlap the transistors and are coupled to the transistors. The second branch lines are formed to branch from the first line in a direction to overlap the diodes and are coupled to the diodes.

Abstract translation: 抑制由于耦合它们的线的电感导致的晶体管的漏极和二极管的阴极之间的切换速度的降低。 在衬底上形成晶体管和二极管。 晶体管和二极管沿第一方向排列。 基板还包括第一线，第一支线和在其上形成的第二支线。 第一条线在晶体管和二极管之间延伸。 第一分支线形成为在与晶体管重叠的方向上从第一行分支并耦合到晶体管。 第二分支线形成为在与二极管重叠的方向上从第一线分支并且耦合到二极管。

公开(公告)号：US20150364467A1

公开(公告)日：2015-12-17

申请号：US14837373

申请日：2015-08-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA

IPC: H01L27/07 ,  H01L29/20 ,  H01L29/423 ,  H01L29/872 ,  H01L29/78

CPC classification number: H01L27/0727 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF.

Abstract translation: 通过使用化合物半导体层（沟道层CNL）形成晶体管SEL。 沟道层CNL形成在缓冲层BUF上。 在晶体管SEL的漏电极DRE，栅电极GE，源电极SOE的第一方向上，埋入电极BE的至少一部分位于与源电极SOE相对的一侧， 栅电极GE。 埋入电极BE连接到晶体管SEL的源极SOE。 埋入电极BE的顶端侵入缓冲层BUF。

公开(公告)号：US20150263002A1

公开(公告)日：2015-09-17

申请号：US14727446

申请日：2015-06-01

Applicant: Renesas Electronics Corporation

Inventor： Akira MATSUMOTO ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L27/088 ,  H01L23/492 ,  H01L27/06 ,  H01L23/528 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20150084135A1

公开(公告)日：2015-03-26

申请号：US14494409

申请日：2014-09-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Takashi NAKAMURA ,  Tadatoshi DANNO

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L24/09 ,  H01L23/4824 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0605 ,  H01L2224/091 ,  H01L2224/45014 ,  H01L2224/48096 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract translation: 源极互连和漏极互连交替地设置在多个晶体管单元之间。 一个接合线在多个点处连接到源互连。 另一个接合线在多个点处连接到源互连。 此外，一个接合线在多个点处连接到漏极互连。 此外，另一个接合线在多个点处连接到漏极互连。