公开(公告)号：US20150006914A1

公开(公告)日：2015-01-01

申请号：US14315486

申请日：2014-06-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke OSHIDA

IPC: G06F12/14

CPC classification number: G06F21/72 ,  G06F21/10 ,  G11B20/00086

Abstract: To raise confidentiality of the value stored in the ROM, in an IC having a built-in or an externally-attached ROM storing a value (program and/or data) encrypted using a predetermined cryptographic key. The IC includes the ROM storing the encrypted value (program and/or data), a unique code generating unit, and a decrypting unit. The unique code generating unit generates a unique code specifically determined by production variation. The decrypting unit calculates a cryptographic key on the basis of the generated unique code and a correction parameter, and decrypts the encrypted value readout from the ROM by using the calculated cryptographic key. The correction parameter is preliminarily calculated outside the IC, on the basis of an initial unique code generated from the unique code generating unit immediately after production of the IC, and the predetermined cryptographic key used for encryption of the value to be stored in the ROM.

Abstract translation: 为了保持存储在ROM中的值的机密性，具有存储使用预定密码密钥加密的值（程序和/或数据）的内置或外部附加ROM的IC。 IC包括存储加密值（程序和/或数据）的ROM，唯一代码生成单元和解密单元。 唯一代码生成单元生成由生产变化专门确定的唯一代码。 解密单元基于生成的唯一码和校正参数来计算密码密钥，并通过使用计算出的加密密钥对从ROM读出的加密值进行解密。 基于从紧随IC生成后的唯一码产生单元生成的初始唯一码以及用于加密要存储在ROM中的值的预定密码密钥，在IC外部预先计算校正参数。

公开(公告)号：US20130207269A1

公开(公告)日：2013-08-15

申请号：US13754014

申请日：2013-01-30

Applicant: Renesas Electronics Corporation

Inventor： Daisuke OSHIDA

IPC: H01L23/488 ,  H01L21/02

CPC classification number: H01L23/5222 ,  A61F13/34 ,  H01L21/02697 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/488 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.

Abstract translation: 其中不对准不会引起短路和布线间电容的半导体器件减少。 多个布线设置在第一层间绝缘层中。 在层中的至少一对布线之间形成气隙。 第二层间绝缘层位于配线和第一层间绝缘层之上。 第二层间绝缘层的第一底面暴露于气隙。 当距离最短的一对相邻布线是第一布线时，第一布线之间的第一层间绝缘层的上端与第一布线侧面接触。 第一个底面低于第一条布线的上面。 b/a@0.5表示第一布线之间的距离，b表示与第一底面接触的第一层间绝缘层的部分的宽度。

公开(公告)号：US20170244594A1

公开(公告)日：2017-08-24

申请号：US15416494

申请日：2017-01-26

Applicant: Renesas Electronics Corporation

Inventor： Shigemasa SHIOTA ,  Takeshi SUNADA ,  Akihiro YAMATE ,  Daisuke OSHIDA

IPC: H04L12/24 ,  G07C5/08 ,  H04L29/06 ,  H04L12/26 ,  H04L29/08

CPC classification number: H04L41/0668 ,  G07C5/0808 ,  H04L41/0645 ,  H04L41/0677 ,  H04L43/0817 ,  H04L43/0852 ,  H04L43/10 ,  H04L43/16 ,  H04L63/123 ,  H04L63/1441 ,  H04L67/12 ,  H04W4/48 ,  H04W12/10 ,  H04W12/12 ,  H04W88/16

Abstract: In an on-vehicle system, the gateway is duplexed, and a countermeasure table is included. The countermeasure table defines a failure phenomenon occurring in communication, an identification method for identifying a factor on whether the failure phenomenon is caused by a failure of the gateway or caused by a security attack on the gateway, and a corresponding countermeasure method. When it is detected that a failure phenomenon has occurred is communication through the gateway, the on-vehicle system determines a factor of the detected failure phenomenon based on the identification method defined in the countermeasure table, and makes countermeasures in accordance with the corresponding countermeasure method.

公开(公告)号：US20170034867A1

公开(公告)日：2017-02-02

申请号：US15159231

申请日：2016-05-19

Applicant: Renesas Electronics Corporation

Inventor： Daisuke OSHIDA

IPC: H04W76/02 ,  H04W72/04

CPC classification number: H04W72/0446 ,  H04L9/3268 ,  H04L9/3297 ,  H04L63/0428 ,  H04L63/068 ,  H04L63/0823 ,  H04L63/123 ,  H04L67/12 ,  H04L2209/84 ,  H04L2463/121 ,  H04W4/02 ,  H04W4/046 ,  H04W4/70 ,  H04W12/04 ,  H04W12/10 ,  H04W12/12 ,  H04W76/16

Abstract: The communication terminal includes a communication interface for acquiring external time information from outside and a non-volatile memory and operates as described below. The communication terminal periodically acquires external time information, encrypts the internal time information calibrated based on the acquired external time information, and thereafter writes the encrypted internal time information into the non-volatile memory. in an initialization sequence after power-on of the communication terminal, the communication terminal reads and decrypts internal time information that is lastly written to the non-volatile memory before the power-on, newly acquires external time information, and verifies validity of the acquired external time information by comparing the acquired external time information with the read internal time information.

Abstract translation: 通信终端包括用于从外部获取外部时间信息的通信接口和非易失性存储器，并且如下所述地进行操作。 通信终端周期性地获取外部时间信息，对基于所获取的外部时间信息校准的内部时间信息进行加密，然后将加密的内部时间信息写入非易失性存储器。 在通信终端上电之后的初始化序列中，通信终端在上电之前读取和解密最后写入非易失性存储器的内部时间信息，新获取外部时间信息，并验证所获取的有效性 通过将获取的外部时间信息与读取的内部时间信息进行比较来获得外部时间信息。

公开(公告)号：US20160072621A1

公开(公告)日：2016-03-10

申请号：US14844175

申请日：2015-09-03

Applicant: Renesas Electronics Corporation

Inventor： Daisuke OSHIDA

IPC: H04L9/00 ,  G06F21/72

CPC classification number: H04L9/002 ,  G06F21/554 ,  G06F21/71 ,  G09C1/00 ,  H04L9/003 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/46

Abstract: In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis.A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.

Abstract translation: 在包括不适合使用调平技术的高速密码计算的数据处理中，通过了解半导体芯片中的功能块的布局，可以防止对特定位置的攻击的防篡改。 攻击的例子包括微观探测，故障注入和电磁波分析。 将并行进行相同的密码计算的多个IC芯片层叠或层叠的半导体装置，进行包括密码计算的数据处理。 比较和验证由多个芯片执行的密码计算的结果的芯片被层压在其元件表面被另一个芯片覆盖的中间层中。 例如，当层叠三个芯片时，由上层和下层夹持的中间层中的芯片具有比较验证功能。

公开(公告)号：US20160065367A1

公开(公告)日：2016-03-03

申请号：US14836787

申请日：2015-08-26

Applicant: Renesas Electronics Corporation

Inventor： Daisuke OSHIDA ,  Yoshiyuki SATO ,  Yasuhiro SAGESAKA ,  Takeshi ITOME

IPC: H04L9/08 ,  H04B1/3822 ,  H04W4/02 ,  H04B1/3827 ,  H04L29/12 ,  H04W12/06

CPC classification number: H04L9/0869 ,  G08G1/096783 ,  G08G1/096791 ,  G08G1/162 ,  H04B1/3822 ,  H04B1/3827 ,  H04L61/2007 ,  H04L61/2053 ,  H04L61/2092 ,  H04L61/6004 ,  H04L61/6068 ,  H04L63/0869 ,  H04L63/0892 ,  H04L63/107 ,  H04L67/12 ,  H04W4/025 ,  H04W12/06

Abstract: Provided is a high-speed and light-weighted authentication system that makes IP address filtering possible and does not impair real-time property even on a network including many and unspecific entities (communication devices). In a communication system that a plurality of communication devices are coupled together such that mutual communication is possible over the network, the communication devices communicate with a server under a secure environment, when authentication has been obtained from the server, random seeds of the same value and individual identifiers are issued to them, each communication device generates the IP address that includes a pseudorandom number and the identifier, and the communication devices establish communication between the communication devices that include the pseudorandom numbers that are mutually the same in their IP addresses.

Abstract translation: 提供了一种高速和轻量化的认证系统，使IP地址过滤成为可能，即使在包括许多和非特定实体（通信设备）的网络上也不会影响实时性。 在多个通信设备耦合在一起的通信系统中，使得可以通过网络进行相互通信，当从服务器获得认证时，通信设备在安全环境下与服务器通信，具有相同值的随机种子 并且向它们发出各个标识符，每个通信设备生成包括伪随机数和标识符的IP地址，并且通信设备在包括在其IP地址中相互相同的伪随机数的通信设备之间建立通信。

公开(公告)号：US20210080330A1

公开(公告)日：2021-03-18

申请号：US17009849

申请日：2020-09-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kan TAKEUCHI ,  Yoshio TAKAZAWA ,  Fumio TSUCHIYA ,  Daisuke OSHIDA ,  Naoya OTA ,  Masaki SHIMADA ,  Shinya KONISHI

IPC: G01K1/02 ,  H02P29/68 ,  G01K7/01 ,  G08C17/02

Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.

公开(公告)号：US20200082128A1

公开(公告)日：2020-03-12

申请号：US16540841

申请日：2019-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke OSHIDA

IPC: G06F21/73

Abstract: A semiconductor device included in a computer system, the semiconductor device comprising an acquiring circuit that acquires irreversible data unique to another semiconductor device, and a detecting circuit that verifies whether the irreversible data of another semiconductor device is inconsistent with previously acquired irreversible data of another semiconductor device and detecting an abnormality of the computer system based on the verification result.

公开(公告)号：US20150004782A1

公开(公告)日：2015-01-01

申请号：US14490011

申请日：2014-09-18

Applicant: Renesas Electronics Corporation

Inventor： Daisuke OSHIDA

IPC: H01L23/522

CPC classification number: H01L23/5222 ,  A61F13/34 ,  H01L21/02697 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/488 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.

Abstract translation: 其中不对准不会引起短路和布线间电容的半导体器件减少。 多个布线设置在第一层间绝缘层中。 在层中的至少一对布线之间形成气隙。 第二层间绝缘层位于布线和第一层间绝缘层之上。 第二层间绝缘层的第一底面暴露于气隙。 当距离最短的一对相邻布线是第一布线时，第一布线之间的第一层间绝缘层的上端与第一布线侧面接触。 第一个底面低于第一条布线的上面。 b / a＆nlE; 0.5，其中a表示第一布线之间的距离，b表示与第一底面接触的第一层间绝缘层的部分的宽度。