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公开(公告)号：US08866686B1
公开(公告)日：2014-10-21
申请号：US13826926
申请日：2013-03-14
Applicant: Raytheon Company
Inventor： Thomas V. Sikina , Gregory M. Fagerlund , Jack J. Schuss , Karen A. Rapoza
CPC classification number: H01P11/00 , H01Q3/40 , H01Q21/0043
Abstract: Methods and apparatus for a super-element assembly including a dielectric subassembly having first and second conductive patch conductors extending a longitudinal axis of the super-element assembly, a ridged waveguide having a series of slots formed along its length. The super-element assembly provides a significant advance in the art in module reduction, production cost reduction, and enhanced scan angle response.
Abstract translation: 一种用于超级元件组件的方法和装置，包括具有延伸超级元件组件的纵向轴线的第一和第二导电贴片导体的介电子组件，脊状波导具有沿其长度形成的一系列槽。 超级元件组件在模块减少，生产成本降低和增强的扫描角响应中提供了本领域的显着进步。
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公开(公告)号：US12021306B2
公开(公告)日：2024-06-25
申请号：US17511153
申请日：2021-10-26
Applicant: Raytheon Company
Inventor： Thomas V. Sikina , John P. Haven , James E. Benedict , Jonathan E. Nufio-Molina , Andrew R. Southworth
IPC: H01Q21/00 , B33Y10/00 , B33Y80/00 , H01P1/04 , H01P5/02 , H01Q1/42 , H01Q1/44 , H01Q1/52 , H01Q13/10 , H01Q13/18 , H01Q17/00 , H05K1/02 , H05K3/40
CPC classification number: H01Q21/0087 , H01P1/047 , H01P5/028 , H01Q1/42 , H01Q1/44 , H01Q1/523 , H01Q1/526 , H01Q13/10 , H01Q13/106 , H01Q13/18 , H01Q17/001 , H01Q17/008 , H01Q21/0075 , H05K1/0219 , H05K3/4038 , B33Y10/00 , B33Y80/00
Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
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公开(公告)号：US11949216B2
公开(公告)日：2024-04-02
申请号：US17658344
申请日：2022-04-07
Applicant: Raytheon Company
Inventor： Channing P. Favreau , Alexander Gilbert , Thomas V. Sikina
CPC classification number: H02G15/10 , H05K5/0247
Abstract: Methods and apparatus for a housing assembly including a housing comprising a conductive material, a conductor extending through the housing, and a dielectric material at least partially surrounding the conductor. Portions of the housing may surround the conductor such that the conductor, the dielectric, and the portions of the housing form a channel through the housing.
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公开(公告)号：US20230121347A1
公开(公告)日：2023-04-20
申请号：US18068578
申请日：2022-12-20
Applicant: RAYTHEON COMPANY
Inventor： Andrew R. Southworth , Thomas V. Sikina , John P. Haven , James E. Benedict , Kevin Wilder
Abstract: Electromagnetic circuit structures and methods are provided for a circuit board that includes a hole disposed through a substrate to provide access to an electrical component, such as a signal trace line (or stripline), that is at least partially encapsulated (e.g., sandwiched) between substrates. The electrical component includes a portion substantially aligned with the hole, and an electrical conductor is disposed within the hole. The electrical conductor is soldered to the portion of the electrical component.
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公开(公告)号：US11632856B2
公开(公告)日：2023-04-18
申请号：US17366836
申请日：2021-07-02
Applicant: RAYTHEON COMPANY
Inventor： Andrew Southworth , Kevin Wilder , James Benedict , Mary K. Herndon , Thomas V. Sikina , John P. Haven
IPC: H05K1/02 , H05K1/11 , H05K1/18 , H05K3/26 , H05K3/30 , H05K5/00 , H05K5/06 , H05K9/00 , H01L23/34 , H01L23/498 , H01L23/552 , H01Q1/38 , H01Q1/52 , H05K3/00
Abstract: A circuit assembly is provided and includes a printed circuit board (PCB) having a circuit element region and defining a trench surrounding an entirety of the circuit element region, a circuit element disposed within the circuit element region of the PCB; and a Faraday wall. The Faraday wall includes a solid, unitary body having a same shape as the trench. The Faraday wall is disposed within the trench to surround an entirety of the circuit element.
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Patent Agency Ranking
公开(公告)号：US11581652B2
公开(公告)日：2023-02-14
申请号：US17578034
申请日：2022-01-18
Applicant: RAYTHEON COMPANY
Inventor： Peter J. Adams , Thomas V. Sikina , John P. Haven , James E. Benedict
Abstract: The concepts, systems, circuits and techniques described herein are directed toward a spiral antenna which may be provided using additive manufacturing technology so as to provide an antenna capable of operation at frequencies which are higher than spiral antennas manufactured using standard photo-etch or printed circuit board (PCB) manufacturing processes.
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公开(公告)号：US11469520B2
公开(公告)日：2022-10-11
申请号：US16786880
申请日：2020-02-10
Applicant: RAYTHEON COMPANY
Inventor： Jack J. Schuss , Phillip W. Thiessen , Thomas V. Sikina
Abstract: A dual band dipole radiator array includes a high band radiator array disposed on a dielectric layer for transmitting and receiving high band radar signals; a low band radiator array disposed on a front side of the high band radiator array for transmitting and receiving low band radar signals; a foam material between the low band radiator array and the high band radiator array for support; and a single aperture for both the low band radiator array and the high band radiator array for transmitting and receiving the radar signals, where the low band radiator array is comprised of a plurality of dipole structures disposed within the foam material and tuned to pass through high band radar signals to or from the high band radiator array.
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公开(公告)号：US20210368629A1
公开(公告)日：2021-11-25
申请号：US17395977
申请日：2021-08-06
Applicant: RAYTHEON COMPANY
Inventor： Mikhail Pevzner , James E. Benedict , Andrew R. Southworth , Thomas V. Sikina , Kevin Wilder , Matthew Souza , Aaron Michael Torberg
Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
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公开(公告)号：US20210359429A1
公开(公告)日：2021-11-18
申请号：US16874790
申请日：2020-05-15
Applicant: Raytheon Company
Inventor： Thomas V. Sikina , John P. Haven , Channing P. Favreau
Abstract: Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region.
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公开(公告)号：US20210305187A1
公开(公告)日：2021-09-30
申请号：US16836470
申请日：2020-03-31
Applicant: RAYTHEON COMPANY
Inventor： James E. Benedict , Paul A. Danello , Mikhail Pevzner , Thomas V. Sikina , Andrew R. Southworth
IPC: H01L23/00
Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
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