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公开(公告)号:US20240179342A1
公开(公告)日:2024-05-30
申请号:US18507544
申请日:2023-11-13
Applicant: QUALCOMM Incorporated
Inventor: Yan Zhang , Han Huang , Vadim Seregin , Marta Karczewicz
IPC: H04N19/52 , H04N19/105 , H04N19/139 , H04N19/176 , H04N19/70
CPC classification number: H04N19/52 , H04N19/105 , H04N19/139 , H04N19/176 , H04N19/70
Abstract: A video coder is configured to receive a first block of video data to be coded using adaptive affine decoder side motion vector refinement (DMVR). The video coder may determine to set a first motion vector difference (MVD) for a first reference picture list to zero, and then refine control point motion vectors (CPMVs) associated with a second reference picture list to generate refined CPMVs. The video coder may then code the first block of video data using the refined CPMVs.
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公开(公告)号:US20240121426A1
公开(公告)日:2024-04-11
申请号:US18467513
申请日:2023-09-14
Applicant: QUALCOMM Incorporated
Inventor: Han Huang , Yan Zhang , Zhi Zhang , Vadim Seregin , Marta Karczewicz
IPC: H04N19/52 , H04N19/105 , H04N19/119 , H04N19/127 , H04N19/139 , H04N19/159 , H04N19/176 , H04N19/56
CPC classification number: H04N19/52 , H04N19/105 , H04N19/119 , H04N19/127 , H04N19/139 , H04N19/159 , H04N19/176 , H04N19/56
Abstract: Encoding and decoding video data using an affine decoder side motion vector derivation (DMVR) mode includes receiving a block of video data to be decoded using the affine DMVR mode, and dividing the block into a plurality of subblocks. A video encoder and video decoder may determine a final offset for the affine DMVR mode using a first subset of the plurality of subblocks. The video encoder and decoder may code the block of video data using the final offset to generate a coded block of video data.
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公开(公告)号:US11528504B2
公开(公告)日:2022-12-13
申请号:US16924884
申请日:2020-07-09
Applicant: QUALCOMM Incorporated
Inventor: Dmytro Rusanovskyy , Yan Zhang
IPC: H04N19/52 , H04N19/176 , H04N19/59
Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine that a size of a current block of the video data is less than a threshold, the current block being a two-dimensional array of samples representing a portion of a picture; determine a set of motion vector prediction candidates for the current block according to the determination that the size of the current block is less than the threshold; select a motion vector predictor of the motion vector prediction candidates for the current block; code motion information of the current block using the motion vector predictor; and code the current block using the motion information.
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公开(公告)号:US20220201315A1
公开(公告)日:2022-06-23
申请号:US17556142
申请日:2021-12-20
Applicant: QUALCOMM Incorporated
Inventor: Zhi Zhang , Han Huang , Chun-Chi Chen , Yan Zhang , Vadim Seregin , Marta Karczewicz
IPC: H04N19/139 , H04N19/176 , H04N19/157 , H04N19/186 , H04N19/132 , H04N19/513
Abstract: Example devices and techniques for multi-pass decoder-side motion vector refinement (DMVR) are disclosed. An example device includes memory configured to store video data and one or more processors coupled to the memory. The one or more processors are configured to apply a multi-pass DMVR to a motion vector for a block of the video data to determine at least one refined motion vector and decode the block based on the at least one refined motion vector. The multi-pass DMVR includes a block-based first pass, a sub-block-based second pass, and a sub-block-based third pass.
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15.
公开(公告)号:US20210329304A1
公开(公告)日:2021-10-21
申请号:US17225801
申请日:2021-04-08
Applicant: QUALCOMM Incorporated
Inventor: Dmytro Rusanovskyy , Adarsh Krishnan Ramasubramonian , Yan Zhang , Marta Karczewicz
IPC: H04N19/70 , H04N19/172 , H04N19/169
Abstract: An example device for processing video data includes memory configured to store the video data and one or more processors implemented in circuitry and coupled to the memory. The one or more processors are configured to parse a first parameter set, the first parameter set being signaled in a bitstream data once per sequence of a group of encoded pictures. The one or more processors are configured to parse one or more dynamic range adjustment (DRA) syntax elements in a second parameter set, the second parameter set being signaled in the bitstream and being related to at least one picture in the group of encoded pictures, wherein the parsing of the one or more DRA syntax elements is not dependent on any syntax element of the first parameter set, and process the at least one picture based on the first parameter set and the second parameter set.
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公开(公告)号:US20210321107A1
公开(公告)日:2021-10-14
申请号:US17223814
申请日:2021-04-06
Applicant: QUALCOMM Incorporated
Inventor: Dmytro Rusanovskyy , Jianle Chen , Yan Zhang , Marta Karczewicz
IPC: H04N19/13 , H04N19/91 , H04N19/70 , H04N19/186 , H04N19/176
Abstract: A method of decoding video data comprises determining, based on a color format of a picture of the video data, which context model from among a first context model and a second context model to use to determine a context increment for a syntax element that indicates a prefix of an x or y coordinate of a last significant transform coefficient of a color component of a block of the picture; and decoding a bin of the syntax element by applying Context Adaptive Binary Arithmetic Coding (CABAC) using a context determined based on the context increment for the syntax element.
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17.
公开(公告)号:US20210281844A1
公开(公告)日:2021-09-09
申请号:US17192335
申请日:2021-03-04
Applicant: QUALCOMM Incorporated
Inventor: Dmytro Rusanovskyy , Yan Zhang
IPC: H04N19/124 , H04N19/186 , H04N19/70
Abstract: An example device for processing video data includes memory configured to store the video data and one or more processors coupled to the memory. The one or more processors are configured to adjust a chroma dynamic range adjustment (DRA) scale value based on a luma DRA scale value and determine a chroma quantization parameter (QP) based on the luma adjusted chroma DRA scale value, wherein the chroma QP comprises an integer component and a fractional component. The one or more processors are configured to determine an integer chroma QP offset based on the integer component and determine a fractional chroma QP offset based on the fractional component. The one or more processors are configured to determine a DRA chroma scale adjustment value based on the integer chroma QP offset and the fractional chroma QP offset and process the video data based on the DRA chroma scale adjustment value.
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公开(公告)号:US20240430484A1
公开(公告)日:2024-12-26
申请号:US18748939
申请日:2024-06-20
Applicant: QUALCOMM Incorporated
Inventor: Hongtao Wang , Han Huang , Vadim Seregin , Nan Hu , Yan Zhang , Marta Karczewicz
IPC: H04N19/70 , H04N19/117 , H04N19/137 , H04N19/159 , H04N19/176 , H04N19/86
Abstract: An example device for decoding video data includes a memory configured to store video data; and a processing system including one or more processors implemented in circuitry, the processing system being configured to: determine that a previously coded block of video data was coded using uni-prediction mode for which a bi-prediction syntax element is not assigned a value; determine that a current block of the video data is to be coded using a bi-prediction mode and that motion information of the current block is to be predicted from the previously coded block, including from the bi-prediction syntax element of the previously coded block; and in response to the bi-prediction syntax element of the previously coded block not having an assigned value, decode the current block using a substitute value for the bi-prediction syntax element.
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公开(公告)号:US12132885B2
公开(公告)日:2024-10-29
申请号:US17823714
申请日:2022-08-31
Applicant: QUALCOMM Incorporated
Inventor: Han Huang , Yan Zhang , Vadim Seregin , Marta Karczewicz
IPC: H04N19/105 , H04N19/159 , H04N19/176 , H04N19/70
CPC classification number: H04N19/105 , H04N19/159 , H04N19/176 , H04N19/70
Abstract: A method of decoding video data may comprise determining merge candidates for a block of video data and determining if a merge candidate of the merge candidates includes an additional inter prediction signal. If a merge candidate includes an additional inter prediction signal, the method may include disabling at least one decoder side motion vector derivation technique for use on a base prediction signal of the block of video data.
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公开(公告)号:US20240129525A1
公开(公告)日:2024-04-18
申请号:US18481055
申请日:2023-10-04
Applicant: QUALCOMM Incorporated
Inventor: Zhi Zhang , Han Huang , Yan Zhang , Patrick Garus , Vadim Seregin , Marta Karczewicz
IPC: H04N19/583 , H04N19/176 , H04N19/186 , H04N19/70
CPC classification number: H04N19/583 , H04N19/176 , H04N19/186 , H04N19/70
Abstract: An example device for decoding video data includes: a memory configured to store video data; and a processing system comprising one or more processors implemented in circuitry, the processing system being configured to: determine whether motion information of a block of video data is for sub-blocks of the block larger than individual pixels of the block or for the individual pixels, the block being associated with data indicating that the block is to be predicted using affine motion compensation; in response to determining that the motion information of the block is for the sub-blocks, perform sub-block-based affine motion compensation to form a prediction block for the block; in response to determining that the motion information is for the individual pixels, perform pixel-based affine motion compensation to form the prediction block for the block; and decode the block using the prediction block.
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