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    Register files for a digital signal processor operating in an interleaved multi-threaded environment
    11.
    发明授权
    Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
    为交错多线程环境中的数字信号处理器注册文件

    公开(公告)号：US09235418B2

    公开(公告)日：2016-01-12

    申请号：US14189313

    申请日：2014-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Muhammad Ahmed ,  Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC: G06F15/76 ,  G06F9/30 ,  G06F7/38 ,  G06F13/00 ,  G06F9/38

    CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    Abstract translation: 处理器设备包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器苍蝇中的每一个包括多个数据读取端口，并且多个寄存器文件中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

    DEDICATED ARITHMETIC ENCODING INSTRUCTION
    12.
    发明申请
    DEDICATED ARITHMETIC ENCODING INSTRUCTION 有权
    专用算术编码指令

    公开(公告)号：US20150349796A1

    公开(公告)日：2015-12-03

    申请号：US14288018

    申请日：2014-05-27

    Applicant: QUALCOMM Incorporated

    Inventor： Bo Zhou ,  Mao Zeng ,  Erich James Plondke ,  Lucian Codrescu ,  Shu Xiao ,  Junchen Du ,  Suhail Jalil

    IPC: H03M7/40

    CPC classification number: H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

    Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

    Abstract translation: 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。

    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
    13.
    发明申请
    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER 审中-公开
    可配置翻译LOOKASIDE BUFFER

    公开(公告)号：US20140068225A1

    公开(公告)日：2014-03-06

    申请号：US14073190

    申请日：2013-11-06

    Applicant: QUALCOMM Incorporated

    Inventor： Erich James Plondke ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Paul D. Bassett

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.

    Abstract translation: 一种特定的方法包括接收至少一个翻译后备缓冲器（TLB）配置指示符。 至少一个TLB配置指示符指示将在TLB处启用的特定数量的条目。 所述方法还包括响应于所述至少一个TLB配置指示符来修改所述TLB的可搜索条目的数量。

    Dedicated arithmetic encoding instruction
    17.
    发明授权
    Dedicated arithmetic encoding instruction 有权
    专用算术编码指令

    公开(公告)号：US09455743B2

    公开(公告)日：2016-09-27

    申请号：US14288018

    申请日：2014-05-27

    Applicant: QUALCOMM Incorporated

    Inventor： Bo Zhou ,  Mao Zeng ,  Erich James Plondke ,  Lucian Codrescu ,  Shu Xiao ,  Junchen Du ,  Suhail Jalil

    IPC: H03M7/00 ,  H03M7/40 ,  G06F9/30 ,  G06F9/38 ,  H04N19/91 ,  H04N19/13

    CPC classification number: H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

    Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

    Abstract translation: 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。

    Data cache way prediction
    18.
    发明授权
    Data cache way prediction 有权
    数据缓存方式预测

    公开(公告)号：US09367468B2

    公开(公告)日：2016-06-14

    申请号：US13741917

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/16 ,  G06F12/08 ,  G06F9/345 ,  G06F9/38

    CPC classification number: G06F12/0864 ,  G06F9/3455 ,  G06F9/3832 ,  G06F2212/6082

    Abstract: In a particular embodiment, a method includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based on the instruction will access the way.

    Abstract translation: 在特定实施例中，一种方法包括识别指令的一种或多种方式预测特性。 该方法还包括基于一个或多个方式预测特征的识别来选择性地读取用于标识与标识数据高速缓存的方式相关联的表的条目的表。 该方法还包括基于该指令来预测数据高速缓存的下一次访问是否将访问的方式。

    PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DATA-INDEXED ACCUMULATORS IN VECTOR REGISTER FILES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA
    19.
    发明申请
    PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DATA-INDEXED ACCUMULATORS IN VECTOR REGISTER FILES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
    使用矢量寄存器文件中的数据索引累加器的矢量处理器和相关电路，方法和计算机可读介质的标量运算的并行化

    公开(公告)号：US20160026607A1

    公开(公告)日：2016-01-28

    申请号：US14486326

    申请日：2014-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Lucian Codrescu ,  Eric Wayne Mahurin

    IPC: G06F15/82 ,  G06F9/30

    CPC classification number: G06F15/82 ,  G06F9/3001 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3012

    Abstract: Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, related circuits, methods, and computer-readable media are disclosed. In one aspect, a vector processor comprises a vector register file providing a plurality of write ports and a plurality of vector registers each providing a plurality of accumulators. The vector processor receives an input data vector. For each of the plurality of write ports, the vector processor executes vector operation(s) for accessing an input data value of the input data vector, and determining, based on the input data value, a register index for a vector register among the plurality of vector registers, and an accumulator index for an accumulator among the plurality of accumulators of the vector register. Based on the register index, a register value is retrieved from the register index, and a scalar operation is performed based on the register value and the accumulator index.

    Abstract translation: 公开了使用向量寄存器文件，相关电路，方法和计算机可读介质中的数据索引累加器的矢量处理器的标量运算的并行化。 一方面，向量处理器包括提供多个写入端口的向量寄存器文件和多个向量寄存器，每个向量寄存器提供多个累加器。 向量处理器接收输入数据向量。 对于多个写入端口中的每一个，向量处理器执行用于访问输入数据向量的输入数据值的向量操作，并且基于输入数据值，确定多个写入端口中的向量寄存器的寄存器索引 矢量寄存器的多个累加器中的累加器的累加器索引。 基于寄存器索引，从寄存器索引检索寄存器值，并且基于寄存器值和累加器索引执行标量运算。

    Overlap checking for a translation lookaside buffer (TLB)
    20.
    发明授权
    Overlap checking for a translation lookaside buffer (TLB) 有权
    翻译后备缓冲区（TLB）的重叠检查

    公开(公告)号：US09208102B2

    公开(公告)日：2015-12-08

    申请号：US13741981

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Suresh K. Venkumahanti ,  Erich J. Plondke ,  Lucian Codrescu ,  Shane M. Mahon ,  Rahul R. Toley ,  Fadi A. Hamdan

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

    Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.

    Abstract translation: 一种装置包括翻译后备缓冲器（TLB）。 TLB包括至少一个条目，其包括条目虚拟地址和对应于条目页面的条目页面大小指示。 该装置还包括被配置为接收输入页面大小指示和与输入页面相对应的输入虚拟地址的输入逻辑。 该装置还包括重叠检查逻辑，其被配置为至少部分地基于条目页面大小指示和输入页面大小指示来确定输入页面是否与入口页面重叠。

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