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1.发明申请REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT 有权用于数字信号处理器的注册表文件在交互式多路径环境中运行公开(公告)号：US20140181468A1
公开(公告)日：2014-06-26
申请号：US14189313
申请日：2014-02-25
Applicant: QUALCOMM Incorporated
Inventor： Muhammad Ahmed , Erich James Plondke , Lucian Codrescu , William C. Anderson
IPC: G06F9/30
CPC classification number: G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。
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2.发明授权Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权为交错多线程环境中的数字信号处理器注册文件公开(公告)号：US09235418B2
公开(公告)日：2016-01-12
申请号：US14189313
申请日：2014-02-25
Applicant: QUALCOMM Incorporated
Inventor： Muhammad Ahmed , Erich James Plondke , Lucian Codrescu , William C. Anderson
CPC classification number: G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
Abstract: A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
Abstract translation: 处理器设备包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器苍蝇中的每一个包括多个数据读取端口，并且多个寄存器文件中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。
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