公开(公告)号：US11907138B2

公开(公告)日：2024-02-20

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral Nandu ,  Subbarao Palacharla ,  George Patsilaras ,  Alain Artieri ,  Simon Peter William Booth ,  Vipul Gandhi ,  Girish Bhat ,  Yen-Kuan Wu ,  Younghoon Kim

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US11682454B2

公开(公告)日：2023-06-20

申请号：US17518485

申请日：2021-11-03

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Mehrad Tavakoli ,  Injoon Hong ,  Huang Huang ,  Simon Peter William Booth ,  Gerhard Reitmayr

IPC: G06F1/3287 ,  G06F3/01 ,  G06F3/14 ,  G06T5/00 ,  G06T19/00 ,  G11C11/419 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/419 ,  G06F1/3287 ,  G06F3/013 ,  G06F3/14 ,  G06T5/006 ,  G06T19/006 ,  G11C11/412 ,  H10B10/12

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

公开(公告)号：US11132208B2

公开(公告)日：2021-09-28

申请号：US16689666

申请日：2019-11-20

Applicant: QUALCOMM Incorporated

Inventor： Matthew Severson ,  Kangmin Lee ,  Cristian Duroiu ,  Simon Peter William Booth ,  Steven Halter

IPC: G06F9/44 ,  G06F1/04 ,  G06F9/445

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

公开(公告)号：US20200250097A1

公开(公告)日：2020-08-06

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： WESLEY JAMES HOLLAND ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0862 ,  G06F12/1009 ,  G06T1/60

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.