公开(公告)号：US20240111424A1

公开(公告)日：2024-04-04

申请号：US18527713

申请日：2023-12-04

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

公开(公告)号：US20220027067A1

公开(公告)日：2022-01-27

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Dexter Tamio CHUN ,  Michael Hawjing LO ,  Shyamkumar THOZIYOOR ,  Ravindra KUMAR

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US20210343331A1

公开(公告)日：2021-11-04

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US20190221252A1

公开(公告)日：2019-07-18

申请号：US16362427

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US20180314586A1

公开(公告)日：2018-11-01

申请号：US15942372

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Alain ARTIERI ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Dexter Tamio CHUN ,  Jungwon SUH

IPC: G06F11/10 ,  G06F3/06

CPC classification number: H04L1/0041 ,  H03M13/19 ,  H04L1/0045 ,  H04L1/0057

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

公开(公告)号：US20160093403A1

公开(公告)日：2016-03-31

申请号：US14499161

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill KIM ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH

IPC: G11C29/00 ,  G06F11/07 ,  G11C11/406 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/78 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/783 ,  G11C29/787

Abstract: In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.

Abstract translation: 在随机存取存储器（RAM）的修复中，接收到错误信息，识别出的RAM的故障地址以及在RAM的内容有效时应用于冗余电路的一部分的一次性编程。 可选地，RAM是动态访问RAM（DRAM），刷新突发被应用于DRAM，随后是非刷新间隔，并且在非刷新间隔期间执行一次性编程。

公开(公告)号：US20150332735A1

公开(公告)日：2015-11-19

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio CHUN ,  Vaishnav SRINIVAS ,  David Ian WEST ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Jason THURSTON

IPC: G11C5/14 ,  G06F11/07

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract translation: 通过多相多路存储器总线通过片上系统（SoC）写入和读取动态随机存取存储器（DRAM）的功耗基于误码率（BER）和一个或多个阈值进行优化。 可以测量误码率（BER）并用于控制参数以实现功耗和精度之间的最佳平衡。 在正常任务模式操作与实时流量期间，执行误码率（BER）测量，有意添加抖动和检查阈值。 错误检测可以涵盖具有二进制数据块的每个存储器数据事务。

公开(公告)号：US20150067234A1

公开(公告)日：2015-03-05

申请号：US14016717

申请日：2013-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Jung Pill KIM ,  Dexter Tamio CHUN ,  Jungwon SUH

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1694

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract translation: 提供增强的多芯片封装（eMCP），包括统一的存储器控​​制器。 UMC被配置为管理不同类型的存储器，例如eMCP上的NAND闪存和DRAM。 联电提供存储内存管理，DRAM管理，存储内存管理的DRAM可访问性和DRAM管理的存储存储器可访问性。 UMC还有助于从DRAM到存储器的直接数据复制，反之亦然。 直接复制可以由UMC发起，而无需与主机的交互，也可以由主机发起。

公开(公告)号：US20250028445A1

公开(公告)日：2025-01-23

申请号：US18354525

申请日：2023-07-18

Applicant: QUALCOMM Incorporated

Inventor： Pankaj DESHMUKH ,  Subbarao PALACHARLA ,  Shyamkumar THOZIYOOR ,  Jungwon SUH ,  Anurag NANNAKA

IPC: G06F3/06

Abstract: Various embodiments include systems and methods for improving the efficiency of a memory subsystem in a computing device. The memory subsystem may be configured to detect memory access events and determining their associated timings and determine an efficiency of the memory subsystem based on operational parameters of the memory subsystem, the detecting memory access events, and associated timings. The memory subsystem may adjust the operational parameters of the memory subsystem based on the determined efficiency of the memory subsystem. The memory subsystem may dynamically modify the operations of the memory subsystem based on the adjusted operational parameters.

公开(公告)号：US20230136996A1

公开(公告)日：2023-05-04

申请号：US17452606

申请日：2021-10-28

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

IPC: G06F3/06

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.