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公开(公告)号：US20170352182A1
公开(公告)日：2017-12-07
申请号：US15174110
申请日：2016-06-06
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Xuefeng Tang , Jian Liang
CPC classification number: G06T15/30 , G06T1/20 , G06T15/005 , G06T15/40 , G06T15/405
Abstract: A graphics processing unit (GPU) may perform a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene, including performing low-resolution z-culling of representations of the plurality of primitives based at least in part on a first set of culling z-values each having a first test size to determine a first set of visible primitives from the plurality of primitives. The GPU may further perform a rendering pass to render the plurality of tiles based at least in part on performing the low-resolution z-culling of representations of the first set of visible primitives based at least in part on a second set of culling z-values that represents a second test size to determine a second set of visible primitives from the first set of visible primitives, wherein the first test size is greater than the second test size.
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公开(公告)号：US11600002B2
公开(公告)日：2023-03-07
申请号：US16892096
申请日：2020-06-03
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Srihari Babu Alla , Kalyan Kumar Bhiravabhatla , Jonnala Gadda Nagendra Kumar , William Licea-Kane , Fredrick Alan Hickman
Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.
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公开(公告)号：US10748239B1
公开(公告)日：2020-08-18
申请号：US16290761
申请日：2019-03-01
Applicant: QUALCOMM Incorporated
Inventor： Nigel Poole , Xuefeng Tang , Jian Liang
Abstract: The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.
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公开(公告)号：US10163180B2
公开(公告)日：2018-12-25
申请号：US14699806
申请日：2015-04-29
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Minjie Huang , Chunlin Wang
Abstract: This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.
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Patent Agency Ranking
公开(公告)号：US20170084043A1
公开(公告)日：2017-03-23
申请号：US14862532
申请日：2015-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Yang Xia , Xuefeng Tang , Jian Liang , Tao Wang , Andrew Evan Gruber , Eric Demers
CPC classification number: G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
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公开(公告)号：US12079897B2
公开(公告)日：2024-09-03
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Rahul Sunil Kukreja , Vishwanath Shashikant Nikam , Tao Wang , Jian Liang
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/405
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20210383545A1
公开(公告)日：2021-12-09
申请号：US16892096
申请日：2020-06-03
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Srihari Babu Alla , Kalyan Kumar Bhiravabhatla , Jonnala Gadda Nagendra Kumar , William Licea-Kane , Fredrick Alan Hickman
Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.
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公开(公告)号：US20200273142A1
公开(公告)日：2020-08-27
申请号：US16282003
申请日：2019-02-21
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Tao Wang , Shangmei Yu , Jing Gao , Jian Liang , Andrew Evan Gruber , Chun Yu
Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.
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公开(公告)号：US09824458B2
公开(公告)日：2017-11-21
申请号：US14862532
申请日：2015-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Yang Xia , Xuefeng Tang , Jian Liang , Tao Wang , Andrew Evan Gruber , Eric Demers
CPC classification number: G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
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