公开(公告)号：US09959665B2

公开(公告)日：2018-05-01

申请号：US14805088

申请日：2015-07-21

Applicant: QUALCOMM Incorporated

Inventor： Nagarjuna Duvvuru ,  Tao Wang ,  Jian Liang ,  Chunlin Wang

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T11/40

CPC classification number: G06T15/40 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/04 ,  G06T2200/12 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.

公开(公告)号：US20160321774A1

公开(公告)日：2016-11-03

申请号：US14699806

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Minjie Huang ,  Chunlin Wang

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.

Abstract translation: 本公开描述了一种自适应存储器地址扫描技术，其基于表面的一个或多个属性定义要用于特定表面的地址扫描图案。 此外，可以确定并行处理的表面的子图元的数量，形状和布置。 在本公开的一个示例中，用于图形处理的存储器访问方法包括：由图形处理单元（GPU）确定表面的属性，由GPU确定基于所确定的特性的存储器地址扫描技术 基于所确定的存储器地址扫描技术，通过GPU执行与存储器中的表面相关联的读取或写入数据中的至少一个。

公开(公告)号：US20140331012A1

公开(公告)日：2014-11-06

申请号：US13928169

申请日：2013-06-26

Applicant: QUALCOMM Incorporated

Inventor： Chunlin Wang

IPC: G06F12/08

CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0855 ,  G06F13/1663 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/62

Abstract: This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

Abstract translation: 本公开涉及对访问高速缓存的不同类型的请求的仲裁。 本公开的特征可以在图形处理单元（GPU）中实现。 在一个实施例中，仲裁器可以接收来自颜色处理器和深度处理器的请求，并确定接收到的请求中哪一个具有最高优先级。 然后可以将具有最高优先级的请求提供给缓存。 优先级可以配置。 仲裁器可以例如基于与请求相关联的缓存中的位置是否可用，与请求相关联的权重，仲裁者处理的特定类型的请求数或其任何组合来确定优先级。

公开(公告)号：US10163180B2

公开(公告)日：2018-12-25

申请号：US14699806

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Minjie Huang ,  Chunlin Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06T11/40

Abstract: This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.

公开(公告)号：US20170024926A1

公开(公告)日：2017-01-26

申请号：US14805088

申请日：2015-07-21

Applicant: QUALCOMM Incorporated

Inventor： Nagarjuna Duvvuru ,  Tao Wang ,  Jian Liang ,  Chunlin Wang

IPC: G06T15/40 ,  G06T15/00

CPC classification number: G06T15/40 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/04 ,  G06T2200/12 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.

Abstract translation: 图形处理单元（GPU）可以包括被配置为确定三角形的坐标的三角形设置引擎（TSE），基于角度旋转三角形的坐标。 为了旋转坐标，TSE在旋转的域中生成三角形的坐标，并根据旋转域中的三角形的坐标确定旋转域中边界框的坐标。 TSE确定旋转域中的第一多个平行扫描线和旋转域中的第二多个并行扫描线。 第一和第二扫描线是垂直的。 TSE确定边界框坐标是否位于两个相邻的扫描线之内。 如果边界框坐标位于两个相邻的扫描线内，则TSE会从场景中删除三角形。

公开(公告)号：US09135179B2

公开(公告)日：2015-09-15

申请号：US13928169

申请日：2013-06-26

Applicant: QUALCOMM Incorporated

Inventor： Chunlin Wang

IPC: G06F12/08

CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0855 ,  G06F13/1663 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/62

Abstract: This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

Abstract translation: 本公开涉及对访问高速缓存的不同类型的请求的仲裁。 本公开的特征可以在图形处理单元（GPU）中实现。 在一个实施例中，仲裁器可以接收来自颜色处理器和深度处理器的请求，并确定接收到的请求中哪一个具有最高优先级。 然后可以将具有最高优先级的请求提供给缓存。 优先级可以配置。 仲裁器可以例如基于与请求相关联的缓存中的位置是否可用，与请求相关联的权重，仲裁者处理的特定类型的请求数或其任何组合来确定优先级。

公开(公告)号：US10289574B2

公开(公告)日：2019-05-14

申请号：US14853891

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Chunlin Wang

IPC: G06F12/08 ,  G06F13/16 ,  G06F12/0855 ,  G06F12/084 ,  G06F12/0842

Abstract: This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

公开(公告)号：US20160004651A1

公开(公告)日：2016-01-07

申请号：US14853891

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Chunlin Wang

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0855 ,  G06F13/1663 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/62

Abstract: This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

Abstract translation: 本公开涉及对访问高速缓存的不同类型的请求的仲裁。 本公开的特征可以在图形处理单元（GPU）中实现。 在一个实施例中，仲裁器可以接收来自颜色处理器和深度处理器的请求，并确定接收到的请求中哪一个具有最高优先级。 然后可以将具有最高优先级的请求提供给缓存。 优先级可以配置。 仲裁器可以例如基于与请求相关联的缓存中的位置是否可用，与请求相关联的权重，仲裁者处理的特定类型的请求数或其任何组合来确定优先级。