公开(公告)号：US10121001B1

公开(公告)日：2018-11-06

申请号：US15629516

申请日：2017-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Satyaki Mukherjee

IPC: G06F7/04 ,  G06F21/55 ,  G06F9/455 ,  G06F9/48

Abstract: Systems for a method for monolithic workload scheduling in a portable computing device (“PCD”) having a hypervisor are disclosed. An exemplary method comprises instantiating a primary virtual machine at a first exception level, wherein the primary virtual machine comprises a monolithic scheduler configured to allocate workloads within and between one or more guest virtual machines in response to one or more interrupts, instantiating a secure virtual machine at the first exception level and instantiating one or more guest virtual machines at the first exception level as well. When an interrupt is received at a hypervisor associated with a second exception level, the interrupt is forwarded to the monolithic scheduler along with hardware usage state data and guest virtual machine usage state data. The monolithic scheduler may, in turn, generate one or more context switches which may comprise at least one intra-VM context switch and at least one inter-VM context switch.

公开(公告)号：US20180121125A1

公开(公告)日：2018-05-03

申请号：US15340895

申请日：2016-11-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0637 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1027 ,  G06F21/53 ,  G06F21/78 ,  G06F2212/50 ,  G06F2212/68 ,  H04L63/02

Abstract: In an aspect, an apparatus obtains, at one or more hardware configuration interfaces, a physical page number associated with a secure resource, a domain identifier, and at least one memory attribute. The one or more hardware configuration interfaces may be in communication with a resource protection unit that manages access to the secure resource. The apparatus configures, by the one or more hardware configuration interfaces, a page table entry in a page table maintained at the resource protection unit, where the page table entry is configured to include the physical page number associated with the secure resource, the domain identifier, and the at least one memory attribute. The resource protection unit processes a resource access transaction when an access permission for the resource access transaction is determined in the page table.

公开(公告)号：US20180024944A1

公开(公告)日：2018-01-25

申请号：US15217728

申请日：2016-07-22

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Mitchel Humpherys

IPC: G06F12/14 ,  G06F12/1009

CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F12/1416 ,  G06F12/145 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/152

Abstract: Disclosed are methods and apparatus for memory management in shared virtual memory (SVM) systems. The methods and apparatus provide SVM access control on a per master basis through the assignment of a first classification identifier (ID) upon reception of a memory access request from a memory master. The assigned first classification ID assigned to the memory request is compared with a second classification ID stored in at least one page table entry of a page table used to manage the SVM system. The page table entry (PTE) corresponds to one or more memory locations of the SVM being requested in the memory access request. SVM system access operations for the memory access request are then denied if the first classification ID does not match the second classification ID, thereby providing added per master access control for the SVM system.

公开(公告)号：US20150127866A1

公开(公告)日：2015-05-07

申请号：US14072201

申请日：2013-11-05

Applicant: Qualcomm Incorporated

Inventor： Thomas ZENG ,  Samar Asbe ,  Azzedine Touzni

IPC: G06F13/26 ,  G06F9/455 ,  G06F13/24

CPC classification number: G06F13/26 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4812 ,  G06F13/24 ,  G06F2009/45579

Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Abstract translation: 方面包括用于安全，快速和正常的虚拟中断直接分配的装置和方法，其通过包括可信（安全）和非安全执行环境的多个执行环境的处理器管理安全和非安全的虚拟和物理中断。 中断控制器可以识别中断的安全组值，并将可靠执行环境直接安全中断。 中断控制器可以识别非安全中断的直接分配值，指示非安全中断是由高级操作系统（HLOS）来宾还是虚拟机管理器（VMM）拥有，以及它是快速还是快速 一个正常的虚拟中断。 在绕过VMM时，中断控制器可以将HLOS Guest拥有的中断指向HLOS Guest。 当HLOS访客不可用时，中断可能被定向到VMM，以尝试将中断传递给HLOS访客，直到成功。

公开(公告)号：US20150067287A1

公开(公告)日：2015-03-05

申请号：US14014288

申请日：2013-08-29

Applicant: Qualcomm Incorporated

Inventor： Azzedine Touzni ,  Thomas Tzeng

IPC: G06F12/14

CPC classification number: G06F21/606 ,  G06F12/1009 ,  G06F12/1475 ,  G06F12/1483 ,  G06F15/167 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052

Abstract: A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.

Abstract translation: 第一处理器和第二处理器被配置为彼此通信安全的处理器间通信（IPC）。 第一个处理器使用第一个内存管理单元（MMU）通过内存系统对安全和非安全的IPC进行路由，从而影响安全的IPC和非安全的IPC。 第一MMU访问存储在存储器系统中的第一页表以路由安全的IPC并访问存储在存储器系统中的第二页表以路由非安全的IPC。 第二个处理器至少使用第二个MMU来保护安全的IPC，以便通过存储系统路由安全的IPC。 第二个MMU访问第二页表以路由安全的IPC。

公开(公告)号：US20140282580A1

公开(公告)日：2014-09-18

申请号：US13834380

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas M. Zeng ,  Azzedine Touzni ,  Thomas Andrew Sartorius

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/12 ,  G06T1/60

Abstract: A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources.

Abstract translation: 无线移动设备包括具有用于保存和恢复系统MMU转换上下文的系统存储器管理单元（MMU）的图形处理单元（GPU）。 系统MMU耦合到存储器和GPU。 系统MMU包括一组硬件资源。 硬件资源可以是上下文库，其中每个上下文库具有一组硬件寄存器。 系统MMU还包括硬件控制器，其被配置为恢复与由GPU的执行线程发布的内容的访问流相关联的硬件资源。 当与内容的访问流相关联的硬件资源不被存储在硬件资源之一内时，相关联的硬件资源可以从存储器恢复为物理硬件资源。

公开(公告)号：US10783252B2

公开(公告)日：2020-09-22

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/445 ,  G06F9/4401 ,  G06F21/51 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

公开(公告)号：US10599442B2

公开(公告)日：2020-03-24

申请号：US15448232

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Dhamim Packer Ali ,  Yanru Li ,  Ashutosh Shrivastava ,  Azzedine Touzni ,  Mamta Desai

IPC: G06F9/4401

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

公开(公告)号：US10310882B2

公开(公告)日：2019-06-04

申请号：US15172529

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Philip Mueller, Jr. ,  Piyush Patel

IPC: G06F9/455 ,  G06F9/50 ,  G06F12/10 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06F21/44 ,  G06F21/53

Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations.

公开(公告)号：US20190065752A1

公开(公告)日：2019-02-28

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F21/57 ,  G06F1/32 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.