公开(公告)号：US10466967B2

公开(公告)日：2019-11-05

申请号：US15224237

申请日：2016-07-29

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Yurong Sun ,  Jianming Zhu ,  Marc Hoffman

IPC: G06F7/483 ,  G06F17/17 ,  G06F9/30 ,  G06F7/544 ,  G06F1/03 ,  G06F7/548

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

公开(公告)号：US20180032311A1

公开(公告)日：2018-02-01

申请号：US15224237

申请日：2016-07-29

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Yurong Sun ,  Jianming Zhu ,  Marc Hoffman

IPC: G06F7/483

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

公开(公告)号：US09268571B2

公开(公告)日：2016-02-23

申请号：US13654730

申请日：2012-10-18

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Marc M. Hoffman ,  Deepak Mathew

IPC: G06F12/00 ,  G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3012

Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Abstract translation: 一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

公开(公告)号：US20140281421A1

公开(公告)日：2014-09-18

申请号：US13842751

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Marc M. Hoffman ,  Ajay Anant Ingle ,  Jose Fridman

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

Abstract translation: 更新输出数据向量的示例方法包括识别包括元素数据值的数据值向量。 该方法还包括识别包括一组元素的地址值向量。 该方法还包括将条件运算符应用于地址值向量中的该组元素的每个元素。 该方法还包括数据值向量中的每个元素数据值，基于应用条件运算符来确定是否更新输出数据向量。

公开(公告)号：US20140281372A1

公开(公告)日：2014-09-18

申请号：US13834785

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  David J. Hoyle ,  Marc M. Hoffman

IPC: G06F15/80

CPC classification number: G06F15/8053 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Abstract translation: 将一个或多个元素数据值放置在输出向量中的示例性方法包括识别包括多个元素的垂直置换控制向量，所述多个元素中的每个元素包括寄存器地址。 该方法还包括对于多个元件的每个元件，从垂直置换控制向量读取寄存器地址。 该方法还包括基于寄存器地址检索多个元素数据值。 该方法还包括识别包括对应于输出向量的一组地址的水平置换控制向量。 该方法还包括基于水平置换控制向量中的地址集合将至少一些所检索到的多个元素数据值的元素数据值放入输出向量中。

公开(公告)号：US08812789B2

公开(公告)日：2014-08-19

申请号：US13894545

申请日：2013-05-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Erich James Plondke ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令，编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。

公开(公告)号：US20140208027A1

公开(公告)日：2014-07-24

申请号：US14219034

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Jian Shen

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0864 ,  G06F17/505 ,  G06F2212/2515 ,  G06F2212/601

Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.

Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。

公开(公告)号：US20140115227A1

公开(公告)日：2014-04-24

申请号：US13654730

申请日：2012-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  Marc M. Hoffman ,  Deepak Mathew

IPC: G06F12/00

CPC classification number: G06F9/30141 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3012

Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Abstract translation: 一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

公开(公告)号：US20130254489A1

公开(公告)日：2013-09-26

申请号：US13894545

申请日：2013-05-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Erich James Plondke ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令，编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。