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公开(公告)号：US12113078B2
公开(公告)日：2024-10-08
申请号：US17479835
申请日：2021-09-20
Inventor： Akito Inoue , Yuki Sugiura , Yutaka Hirose
IPC: H01L27/146 , H04N25/75
CPC classification number: H01L27/1461 , H01L27/14603 , H01L27/14643 , H04N25/75
Abstract: A photodetector includes: a semiconductor substrate having a first main surface and a second main surface; a first semiconductor layer that is of a first conductivity type, and is included in the semiconductor substrate and closer to the first main surface than to the second main surface; a second semiconductor layer that is of a second conductivity type different from the first conductivity type, and is included in the semiconductor substrate and interposed between the first semiconductor layer and the second main surface; a multiplication region that causes avalanche multiplication to a charge generated in the semiconductor substrate through photoelectric conversion; a circuit region disposed alongside the first semiconductor layer in a direction parallel to the first main surface; at least one isolation transistor disposed in the circuit region; and an isolation region interposed between the first semiconductor layer and the circuit region.
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12.发明授权公开(公告)号：US12044573B2
公开(公告)日：2024-07-23
申请号：US17015603
申请日：2020-09-09
Inventor： Toru Okino , Yutaka Hirose
IPC: G01J5/00
CPC classification number: G01J5/0018 , G01J2005/0077
Abstract: A flame detection system includes a determiner and an outputter. The determiner is configured to, when image processing performed on image data detects ultraviolet light, determine that a light emitting source is a fire flame. The outputter is configured to output a determination result by the determiner.
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公开(公告)号：US10923614B2
公开(公告)日：2021-02-16
申请号：US15328648
申请日：2015-07-09
Inventor： Yusuke Sakata , Manabu Usuda , Mitsuyoshi Mori , Yutaka Hirose , Yoshihisa Kato
IPC: H01L31/107 , H01L27/146 , H02S40/44
Abstract: A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p− type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p− type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p− type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p− type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p− type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.
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14.发明授权公开(公告)号：US09799992B2
公开(公告)日：2017-10-24
申请号：US14823659
申请日：2015-08-11
Inventor： Yutaka Hirose , Yoshihisa Kato , Hiroyuki Mori , Taichi Sato , Yoshihide Sawada , Tsuyoshi Tanaka
IPC: G01N1/30 , H01R13/64 , G02B21/34 , F16M11/04 , F16M11/10 , H01R13/639 , H01R13/73 , H04N1/031 , H04N5/372 , B01L9/00 , H04N5/225 , H01L27/146 , H01L27/148 , G02B21/00
CPC classification number: H01R13/64 , B01L9/52 , B01L2300/0645 , B01L2300/0654 , B01L2300/0822 , F16M11/046 , F16M11/10 , G02B21/0008 , G02B21/34 , H01L27/14623 , H01L27/14818 , H01R13/639 , H01R13/73 , H04N1/0315 , H04N1/0318 , H04N5/2257 , H04N5/372
Abstract: A socket includes a first base member that includes a module mount unit allowing a module including an imaging device and an object to be placed thereon and an electric connector that electrically connects the imaging device to an external apparatus, a second base member having an opening, and an engagement unit that causes the first base member to be engaged with the second base member under a condition that the module placed on the module mount unit is sandwiched by the first and second base members. When the first base member is engaged with the second base member by the engagement unit under a condition that the module placed on the module mount unit is sandwiched by the first base member and the second base member, the electric connector is electrically connected to the imaging device, and the object receives illumination light from a light source through the opening.
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公开(公告)号：US09627431B2
公开(公告)日：2017-04-18
申请号：US14572046
申请日：2014-12-16
Inventor： Mitsuyoshi Mori , Ryohei Miyagawa , Yoshiyuki Ohmori , Yoshihiro Sato , Yutaka Hirose , Yusuke Sakata , Toru Okino
IPC: H01L27/146 , H01L27/30
CPC classification number: H01L27/14636 , H01L27/1461 , H01L27/14612 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14645 , H01L27/307
Abstract: A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.
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Patent Agency Ranking
公开(公告)号：US11233958B2
公开(公告)日：2022-01-25
申请号：US16377855
申请日：2019-04-08
Inventor： Yoshiaki Satou , Shota Yamada , Masashi Murakami , Yutaka Hirose
Abstract: An imaging device includes a semiconductor substrate that includes a first impurity region having n-type conductivity; a photoelectric converter that is electrically connected to the first impurity region and that converts light into charges; a capacitor that includes a first terminal and a second terminal, the first terminal being electrically connected to the first impurity region; and a voltage supply circuit electrically connected to the second terminal. The voltage supply circuit is configured to generate a first voltage and a second voltage different from the first voltage. The first impurity region accumulates positive charges generated by the photoelectric converter.
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公开(公告)号：US10212371B2
公开(公告)日：2019-02-19
申请号：US14714366
申请日：2015-05-18
Inventor： Motonori Ishii , Yoshiyuki Matsunaga , Yutaka Hirose
IPC: H01L27/00 , H04N5/363 , H04N5/374 , H04N5/378 , H04N5/3745
Abstract: A solid-state imaging apparatus has: a signal readout circuit including a charge storage region connected to a photoelectric conversion region, and a reset transistor connected at one of source and drain to the charge storage region; and a negative feedback circuit that feeds back an output of the signal readout circuit in a negative feedback manner to the other of the source and drain of the reset transistor. A reset operation for discharging a charge stored in the charge storage region includes a first period in which the negative feedback circuit is OFF and a second period which occurs after the first period and in which the negative feedback circuit is ON. In the first period, the reset transistor changes from OFF to ON and then to OFF. In the second period, such a reset transistor control voltage is applied that makes the reset transistor to gradually change to ON.
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公开(公告)号：US10129494B2
公开(公告)日：2018-11-13
申请号：US15900037
申请日：2018-02-20
Inventor： Motonori Ishii , Yutaka Hirose , Shota Yamada
IPC: H04N5/365 , H04N5/374 , H01L27/146
Abstract: An imaging device includes: a solid-state image sensor including: a plurality of pixels that are arranged in a two-dimensional array; and a signal processing device that processes an output signal from the solid-state image sensor. The imaging device generates a corrected image by: generating a correction signal based on a difference between a first temporary correction signal and a second temporary correction signal, the first temporary correction signal being obtained by directly applying a first voltage amplitude to a signal storage provided in each of the plurality of pixels, and the second temporary correction signal being obtained by applying, to the signal storage, a second voltage amplitude that is different from the first voltage amplitude; acquiring an image signal upon a photographing drive operation being performed by the solid-state image sensor; and applying the correction signal to the image signal.
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公开(公告)号：US09554067B2
公开(公告)日：2017-01-24
申请号：US14723498
申请日：2015-05-28
Inventor： Keisuke Yazawa , Motonori Ishii , Yutaka Hirose , Yoshihisa Kato , Yoshiyuki Matsunaga
IPC: H04N5/363 , H04N5/374 , H04N5/378 , H04N5/3745 , H01L27/30
CPC classification number: H04N5/363 , H01L27/307 , H04N5/374 , H04N5/3741 , H04N5/3745 , H04N5/378
Abstract: The present invention provides a solid-state imaging apparatus that can significantly reduce kTC noise by using a negative feedback amplifying circuit. A solid-state imaging apparatus includes a pixel unit including a plurality of pixels arranged on a semiconductor substrate in a matrix, the pixel unit including, for each column, a source line and a column signal line, each of the plurality of pixels including: a photoelectric conversion unit that generates a signal charge corresponding to incident light; a storage unit storing the signal charge; a reset transistor; an amplifying transistor; and a cutoff transistor, wherein the amplifying transistor and the cutoff transistor form a negative feedback amplifying circuit. With this configuration, kTC noise can significantly be reduced.
Abstract translation: 本发明提供一种可以通过使用负反馈放大电路来显着降低kTC噪声的固态成像装置。 一种固态成像装置，包括：像素单元，包括以矩阵形式布置在半导体衬底上的多个像素，所述像素单元包括：对于每一列，源极线和列信号线，所述多个像素包括： 光电转换单元，其生成与入射光对应的信号电荷; 存储单元，存储所述信号电荷; 复位晶体管; 放大晶体管; 和截止晶体管，其中放大晶体管和截止晶体管形成负反馈放大电路。 通过这种配置，可以显着降低kTC噪声。
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公开(公告)号：US12088946B2
公开(公告)日：2024-09-10
申请号：US17679942
申请日：2022-02-24
Inventor： Shota Yamada , Shigetaka Kasuga , Motonori Ishii , Akito Inoue , Yutaka Hirose
IPC: H04N25/778 , G01S7/481 , G01S7/4865 , G01S17/894 , H04N25/771
CPC classification number: H04N25/778 , G01S7/4816 , G01S7/4865 , G01S17/894 , H04N25/771
Abstract: An imaging device includes: a solid-state imaging element having a plurality of pixel cells arranged in a matrix; and a control part configured to control the solid-state imaging element. The pixel cells each include an avalanche photodiode, a floating diffusion part configured to accumulate electric charges, a transfer transistor connecting a cathode of the avalanche photodiode and the floating diffusion part, and a reset transistor for resetting electric charges accumulated in the floating diffusion part. The control part controls the reset transistor to discharge electric charges exceeding a predetermined electric charge amount, of electric charges accumulated in the floating diffusion part from the cathode of the avalanche photodiode via the transfer transistor.
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