公开(公告)号：US20200258933A1

公开(公告)日：2020-08-13

申请号：US16859623

申请日：2020-04-27

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuko NISHIMURA ,  Yutaka ABE ,  Masashi MURAKAMI ,  Yoshiyuki MATSUNAGA

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/363 ,  H04N5/357

Abstract: An imaging device having a pixel including: a photoelectric converter that generates an electric signal through photoelectric conversion of incident light; a first transistor that has a gate coupled to the photoelectric converter and that amplifies the electric signal; and a second transistor that has a gate coupled to the photoelectric converter, one of a source and a drain of the second transistor being coupled to the photoelectric converter. The imaging device further includes a voltage supply circuit configured to supply two or more different voltages to the other of the source and the drain of the second transistor.

公开(公告)号：US20190259793A1

公开(公告)日：2019-08-22

申请号：US16401974

申请日：2019-05-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masashi MURAKAMI ,  Kazuko NISHIMURA ,  Yutaka ABE ,  Yoshiyuki MATSUNAGA ,  Yoshihiro SATO ,  Junji HIRASE

IPC: H01L27/146

Abstract: An imaging device includes a photoelectric converter that includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, a first transistor that has a gate connected to the first electrode, and a first capacitor and a switching element that are connected, in series, between the first electrode and either a voltage source or a ground.

公开(公告)号：US20250080870A1

公开(公告)日：2025-03-06

申请号：US18951132

申请日：2024-11-18

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Motonori ISHII ,  Yoshiyuki MATSUNAGA ,  Yutaka HIROSE

IPC: H04N25/65 ,  H04N25/75 ,  H04N25/767 ,  H04N25/77

Abstract: An imaging device including a photoelectric converter that generates signal charge; a charge storage region that stores the signal charge; a first transistor that has a gate coupled to the charge storage region and reads out the signal charge; a feedback amplifier that feeds back an output of the first transistor in a negative feedback manner to the charge storage region, the feedback amplifier having two input terminals, the output of the first transistor being input to a first input terminal, a reference voltage being input to a second input terminal; and voltage supply circuitry. In a reset operation for discharging the signal charge stored in the charge storage region, the voltage supply circuitry supplies voltages to the second input terminal of the feedback amplifier, and the voltages include at least three voltages different from each other.

公开(公告)号：US20180114811A1

公开(公告)日：2018-04-26

申请号：US15850645

申请日：2017-12-21

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshihiro SATO ,  Ryohei MIYAGAWA ,  Tokuhiko TAMAKI ,  Junji HIRASE ,  Yoshiyuki OHMORI ,  Yoshiyuki MATSUNAGA

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/363 ,  H01L21/266 ,  H01L21/8234

CPC classification number: H01L27/14643 ,  H01L21/266 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14665 ,  H01L27/14689 ,  H04N5/363 ,  H04N5/378

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

公开(公告)号：US20150123180A1

公开(公告)日：2015-05-07

申请号：US14556093

申请日：2014-11-28

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshihiro SATO ,  Ryohei MIYAGAWA ,  Tokuhiko TAMAKI ,  Junji HIRASE ,  Yoshiyuki OHMORI ,  Yoshiyuki MATSUNAGA

IPC: H01L27/146 ,  H01L21/266 ,  H01L21/8234

CPC classification number: H01L27/14643 ,  H01L21/266 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14665 ,  H01L27/14689 ,  H04N5/363 ,  H04N5/378

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

Abstract translation: 每个单位像素包括光电转换器，与半导体区域一起形成累积二极管的n型杂质区域，累积二极管累积由光电转换器产生的信号电荷;放大器晶体管，包括电连接到杂质区的栅电极 以及形成在放大晶体管周围并注入p型杂质的隔离区域。 放大器晶体管包括形成在栅极电极和隔离区域之间的n型源极/漏极区域和形成在栅电极下方的沟道区域。 在包括沟道区域的部分中，隔离区域中的间隙在栅极宽度方向上比在包括源极/漏极区域的部分处更宽。