公开(公告)号：US20210351768A1

公开(公告)日：2021-11-11

申请号：US16867399

申请日：2020-05-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Liang Zuo ,  Nijun Jiang ,  Min Qu ,  Xuelian Liu

IPC: H03K4/06 ,  H03M3/00 ,  H03M1/56 ,  H04N5/378

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

公开(公告)号：US12294796B2

公开(公告)日：2025-05-06

申请号：US18295207

申请日：2023-04-03

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Chengcheng Xu ,  Lihang Fan ,  Eiichi Funatsu

IPC: H04N5/335 ,  G02B5/20 ,  H04N25/13 ,  H04N25/44 ,  H04N25/704 ,  H04N25/78

Abstract: An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.

公开(公告)号：US12200389B2

公开(公告)日：2025-01-14

申请号：US18322408

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Jiayu Guo ,  Liang Zuo ,  Lihang Fan

IPC: H04N25/78 ,  H03K3/037 ,  H03K5/22 ,  H03K5/24 ,  H03K19/20 ,  H04N25/616

Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

公开(公告)号：US20240334085A1

公开(公告)日：2024-10-03

申请号：US18295207

申请日：2023-04-03

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Chengcheng Xu ,  Lihang Fan ,  Eiichi Funatsu

IPC: H04N25/704 ,  G02B5/20 ,  H04N25/13 ,  H04N25/44 ,  H04N25/78

CPC classification number: H04N25/704 ,  G02B5/201 ,  H04N25/134 ,  H04N25/44 ,  H04N25/78

Abstract: An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.

公开(公告)号：US12088937B2

公开(公告)日：2024-09-10

申请号：US17658559

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Rui Wang ,  Lihang Fan

IPC: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

CPC classification number: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

公开(公告)号：US11991458B2

公开(公告)日：2024-05-21

申请号：US17934196

申请日：2022-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Nijun Jiang ,  Rui Wang

IPC: H04N25/75 ,  H03M1/12 ,  H03M1/18 ,  H04N23/76 ,  H04N25/78

CPC classification number: H04N23/76 ,  H03M1/12 ,  H03M1/18 ,  H03M1/183 ,  H04N25/75 ,  H04N25/78

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.

公开(公告)号：US11683602B1

公开(公告)日：2023-06-20

申请号：US17716856

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Lihang Fan

IPC: H04N25/615 ,  H04N25/133 ,  H04N25/13 ,  H04N25/447

CPC classification number: H04N25/6153 ,  H04N25/133 ,  H04N25/134 ,  H04N25/447

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.