公开(公告)号：US20160111468A1

公开(公告)日：2016-04-21

申请号：US14515307

申请日：2014-10-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Yin Qian ,  Dyson H. Tai ,  Jin Li ,  Chen-Wei Lu ,  Howard E. Rhodes

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L27/1469

Abstract: A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.

Abstract translation: 制造图像传感器的方法包括在形成像素阵列之后，在半导体衬底的成像区域中形成像素阵列并在半导体衬底的周边区域中形成沟槽。 周边区域位于成像区域的周边。 沟槽填充绝缘材料。 在用绝缘材料填充沟槽之后形成互连层。 第一晶片结合到第二晶片。 第一晶片包括互连层和半导体衬底。 半导体衬底的背面变薄以露出绝缘材料。 通过绝缘材料形成通孔。 通孔腔向下延伸到第二晶片的第二互连层。 通孔腔填充导电材料以形成通孔。 绝缘材料使导电材料与半导体衬底绝缘。

公开(公告)号：US09305962B2

公开(公告)日：2016-04-05

申请号：US14528991

申请日：2014-10-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Gang Chen ,  Ashish Shah ,  Duli Mao ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14605 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

公开(公告)号：US09054007B2

公开(公告)日：2015-06-09

申请号：US13968210

申请日：2013-08-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sing-Chung Hu ,  Rongsheng Yang ,  Gang Chen ,  Howard E. Rhodes ,  Sohei Manabe ,  Hsin-Chih Tai

IPC: H01L27/146 ,  H01L27/092

CPC classification number: H01L27/14643 ,  H01L27/0928 ,  H01L27/14601 ,  H01L27/1463 ,  H01L27/1464

Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

Abstract translation: 像素单元包括设置在半导体材料的第一区域中的外延层中的光电二极管。 浮置扩散部设置在设置在第一区域的外延层中的阱区域中。 传输晶体管设置在第一区域中并且耦合在光电二极管和浮动扩散之间以选择性地将图像电荷从光电二极管转移到浮动扩散。 在DTI结构内部布置有介电层的深沟槽隔离（DTI）结构设置在半导体材料中，将DTI结构的一侧上的第一区域与DTI结构的另一侧上的半导体材料的第二区域隔离开 。 响应于传输晶体管选择性地将图像电荷从光电二极管转移到浮动扩散，DTI结构内部的掺杂半导体材料选择性地耦合到读出脉冲电压。

公开(公告)号：US20150048427A1

公开(公告)日：2015-02-19

申请号：US13968210

申请日：2013-08-15

Applicant: Omnivision Technologies, Inc.

Inventor： Sing-Chung Hu ,  Rongsheng Yang ,  Gang Chen ,  Howard E. Rhodes ,  Sohei Manabe ,  Hsin-Chih Tai

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/0928 ,  H01L27/14601 ,  H01L27/1463 ,  H01L27/1464

Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

Abstract translation: 像素单元包括设置在半导体材料的第一区域中的外延层中的光电二极管。 浮置扩散部设置在设置在第一区域的外延层中的阱区域中。 传输晶体管设置在第一区域中并且耦合在光电二极管和浮动扩散之间以选择性地将图像电荷从光电二极管转移到浮动扩散。 在DTI结构内部布置有介电层的深沟槽隔离（DTI）结构设置在半导体材料中，将DTI结构的一侧上的第一区域与DTI结构的另一侧上的半导体材料的第二区域隔离开 。 响应于传输晶体管选择性地将图像电荷从光电二极管转移到浮动扩散，DTI结构内部的掺杂半导体材料选择性地耦合到读出脉冲电压。

公开(公告)号：US20140319639A1

公开(公告)日：2014-10-30

申请号：US14331646

申请日：2014-07-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Howard E. Rhodes ,  Dajiang Yang ,  Gang Chen ,  Duli Mao ,  Vincent Venezia

IPC: H01L27/146

CPC classification number: H01L31/0224 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14643 ,  H01L31/103

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the first polarity charge layer.

Abstract translation: 图像传感器像素包括设置在半导体层中的具有第一极性掺杂型的光电二极管区域。 具有第二极性掺杂型的钉扎表面层设置在半导体层中的光电二极管区域的上方。 第二极性与第一极性相反。 第一极性电荷层设置在光电二极管区域附近的钉扎表面层附近。 接触蚀刻停止层设置在靠近第一极性电荷层的光电二极管区域的上方。 第一极性电荷层设置在钉扎表面层和接触蚀刻停止层之间，使得第一极性电荷层抵消在接触蚀刻停止层中感应的具有第二极性的电荷。 钝化层也设置在钉扎表面层和第一极性电荷层之间的光电二极管区域之上。

公开(公告)号：US20140312447A1

公开(公告)日：2014-10-23

申请号：US14319807

申请日：2014-06-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Duli Mao ,  Dyson H. Tai ,  Vincent Venezia ,  Yin Qian ,  Gang Chen ,  Howard E. Rhodes

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/14623 ,  H01L27/1464 ,  H01L27/14685

Abstract: A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element.

Abstract translation: 背面照明图像传感器包括设置在半导体层中的半导体层和沟槽。 半导体层具有前表面和背面。 半导体层包括设置在半导体层的传感器阵列区域中的像素阵列的光感测元件。 像素阵列被定位成接收穿过半导体层的背面的外部入射光。 半导体层还包括设置在传感器阵列区域外部的半导体层的外围电路区域中的发光元件。 沟槽设置在光感测元件和发光元件之间的半导体层中。

公开(公告)号：US20140220713A1

公开(公告)日：2014-08-07

申请号：US14093802

申请日：2013-12-02

Applicant: Omnivision Technologies Inc.

Inventor： Edward R. Dowski, JR. ,  Paulo E.X. Silvieri ,  George C. Bames, IV ,  Vladislav V. Chumachenko ,  Dennis W. Dobbs ,  Regis S. Fan ,  Gregory E. Johnson ,  Miodrag Scepanovic ,  Satoru Tachihara ,  Christopher J. Linnen ,  Inga Tamayo ,  Donald Combs ,  Howard E. Rhodes ,  James He ,  John J. Mader ,  Goran M. Rauker ,  Kenneth Kubala ,  Mark Meloni ,  Brian Schwartz ,  Robert Cormack ,  Michael Hepp ,  Kenneth Ashley Macon ,  Gary L. Duerksen

IPC: H01L27/146 ,  G06F17/50

CPC classification number: G06F17/504 ,  B24B13/06 ,  B24B49/00 ,  G02B3/0025 ,  G02B3/0031 ,  G02B3/0068 ,  G02B3/0075 ,  G02B7/022 ,  G02B13/0025 ,  G02B13/006 ,  G02B13/0085 ,  G02B27/0025 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2924/0002 ,  H04N5/2257 ,  H01L2924/00

Abstract: Arrayed imaging systems include an array of detectors formed with a common base and a first array of layered optical elements, each one of the layered optical elements being optically connected with a detector in the array of detectors.

Abstract translation: 阵列成像系统包括形成有公共基底和分层光学元件的第一阵列的检测器阵列，每个分层光学元件与检测器阵列中的检测器光学连接。

公开(公告)号：US20140210028A1

公开(公告)日：2014-07-31

申请号：US13754465

申请日：2013-01-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC: H01L27/146 ,  G02B5/20

CPC classification number: G02B5/201 ,  G02B1/105 ,  G02B1/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685

Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Abstract translation: 包括形成在其上形成有像素阵列的基板上的滤色器装置的装置的实施例。 滤色器装置包括具有形成在其上的第一透明硬掩模层和第二透明硬掩模层的透明滤光器，具有形成在其上的第一透明硬掩模层和第二硬掩模层的第一滤色器，具有第二透明硬掩模层的第二滤色器， 形成在其上的第一透明硬掩模层和形成有透明硬掩模层的第三滤色器。 公开和要求保护其他实施例。

公开(公告)号：US08759934B2

公开(公告)日：2014-06-24

申请号：US13649953

申请日：2012-10-11

Applicant: Omnivision Technologies, Inc.

Inventor： Hsin-Chih Tai ,  Howard E. Rhodes ,  Wei Zheng ,  Vincent Venezia ,  Yin Qian ,  Duli Mao

IPC: H01L21/00

CPC classification number: H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14638

Abstract: An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region.

Abstract translation: 图像传感器包括设置在半导体层内的感光区域和应力调整层。 感光区域对于通过图像传感器的第一侧入射的光敏感，以收集图像电荷。 应力调整层设置在半导体层的第一侧上，以建立鼓励光电荷载流子向光敏区迁移的应力特性。

公开(公告)号：US08729712B2

公开(公告)日：2014-05-20

申请号：US14052944

申请日：2013-10-14

Applicant: OmniVision Technologies, Inc.

Inventor： Yin Qian ,  Dyson H. Tai ,  Keh-Chiang Ku ,  Vincent Venezia ,  Duli Mao ,  Wei Zheng ,  Howard E. Rhodes

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L23/522 ,  H01L24/05 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/6835 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract translation: 半导体器件的实施例包括半导体衬底和设置在半导体衬底中的至少从半导体衬底的第一侧至半导体衬底的第二侧延伸的空腔。 半导体器件还包括设置在半导体衬底的第一侧上并涂覆空腔的侧壁的绝缘层。 包括接合焊盘的导电层设置在绝缘层上。 导电层延伸到空腔中并且连接到设置在半导体衬底的第二侧下方的金属叠层。 贯穿硅通孔焊盘设置在半导体衬底的第二侧下方并连接到金属堆叠。 贯穿硅通孔焊盘的位置是接受硅通孔。