公开(公告)号：US20100163116A1

公开(公告)日：2010-07-01

申请号：US12422690

申请日：2009-04-13

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： F16L53/00 ,  B44C1/22

CPC分类号： B41J2/1601 ,  B41J2/14056 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2002/1437 ,  B41J2202/16 ,  Y10T137/6416

摘要： A method that includes forming a chamber in a substrate, forming a silicon layer overlying the chamber, etching the silicon layer to remove selected regions and retain a selected portion overlying the chamber, the selected portion being at a location and having dimensions that correspond to a location and to dimensions of a nozzle, and forming a first metal layer adjacent to the selected portion. The method also includes forming a path in the substrate to expose the chamber concurrently with removing the selected portion of the silicon layer to expose the nozzle, the nozzle being in fluid communication with the path, the chamber, and a surrounding environment.

摘要翻译： 一种方法，其包括在衬底中形成腔室，形成覆盖在所述腔室上的硅层，蚀刻所述硅层以去除所选择的区域并且保持覆盖所述腔室的选定部分，所述选定部分位于并且具有对应于 位置和尺寸，以及形成与选定部分相邻的第一金属层。 该方法还包括在衬底中形成路径以同时去除硅层的选定部分以暴露喷嘴，喷嘴与路径，腔室和周围环境流体连通。

公开(公告)号：US20060071149A1

公开(公告)日：2006-04-06

申请号：US10955722

申请日：2004-09-30

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： H01L31/00

CPC分类号： H01L33/20 ,  G02B3/00 ,  H01L31/02327 ,  H01L33/58

摘要： A semiconductor device includes a semiconductor material substrate, an opto-electric component formed on the substrate, and a first transparent layer formed on an upper surface of the substrate over the component, the layer having a planar upper surface with a cavity formed therein. The first transparent layer has a selected thickness and a first index of refraction. The semiconductor device further includes a lens having a second index of refraction, the lens being formed in the cavity and having a planar upper surface. An upper surface of the lens and the upper surface of the transparent layer may be coplanar, or alternatively, they may lie in separate planes. The semiconductor device may also include a second transparent layer formed over the first layer and lens, as a passivation layer. The first transparent layer may be silicon dioxide, while the lens may be a flowable dielectric.

摘要翻译： 半导体器件包括半导体材料基板，形成在基板上的光电部件和形成在该部件上的基板的上表面上的第一透明层，该层具有形成在其中的空腔的平面上表面。 第一透明层具有选定的厚度和第一折射率。 所述半导体器件还包括具有第二折射率的透镜，所述透镜形成在所述空腔中并且具有平坦的上表面。 透镜的上表面和透明层的上表面可以是共面的，或者可以位于分开的平面中。 半导体器件还可以包括形成在第一层和透镜上的第二透明层作为钝化层。 第一透明层可以是二氧化硅，而透镜可以是可流动的电介质。

公开(公告)号：US08925835B2

公开(公告)日：2015-01-06

申请号：US12422690

申请日：2009-04-13

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： B05B1/24 ,  B41J2/16 ,  B41J2/14

CPC分类号： B41J2/1601 ,  B41J2/14056 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2002/1437 ,  B41J2202/16 ,  Y10T137/6416

摘要： A method that includes forming a chamber in a substrate, forming a silicon layer overlying the chamber, etching the silicon layer to remove selected regions and retain a selected portion overlying the chamber, the selected portion being at a location and having dimensions that correspond to a location and to dimensions of a nozzle, and forming a first metal layer adjacent to the selected portion. The method also includes forming a path in the substrate to expose the chamber concurrently with removing the selected portion of the silicon layer to expose the nozzle, the nozzle being in fluid communication with the path, the chamber, and a surrounding environment.

摘要翻译： 一种方法，其包括在衬底中形成腔室，形成覆盖在所述腔室上的硅层，蚀刻所述硅层以去除所选择的区域并且保持覆盖所述腔室的选定部分，所述选定部分位于并且具有对应于 位置和尺寸，以及形成与选定部分相邻的第一金属层。 该方法还包括在衬底中形成路径以同时去除硅层的选定部分以暴露喷嘴，喷嘴与路径，腔室和周围环境流体连通。

公开(公告)号：US08798448B2

公开(公告)日：2014-08-05

申请号：US12968150

申请日：2010-12-14

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： F24H1/20

CPC分类号： B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

摘要： An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

摘要翻译： 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

公开(公告)号：US07964474B2

公开(公告)日：2011-06-21

申请号：US12422723

申请日：2009-04-13

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： H01L21/76

CPC分类号： B81C1/00047 ,  B01L3/502707 ,  B01L7/00 ,  B41J2/14129 ,  B41J2/14137 ,  B41J2202/13 ,  B81B2201/058 ,  B81B2207/015 ,  G01L9/0042 ,  G01L9/0098 ,  G01P15/0802 ,  G01P2015/0828

摘要： A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region.

摘要翻译： 一种方法包括与衬底中的第二氧化物区域同时生长第一氧化物区域并形成到第一氧化物区域的入口路径，入口路径暴露第一氧化物区域的第一表面。 该方法还包括去除第一氧化物区域以形成室，形成与第二氧化物区域相邻的第一MOS晶体管，以及通过第二氧化物区域形成与第一MOS晶体管分离的第二MOS晶体管。

公开(公告)号：US20100167497A1

公开(公告)日：2010-07-01

申请号：US12422723

申请日：2009-04-13

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： H01L21/311

CPC分类号： B81C1/00047 ,  B01L3/502707 ,  B01L7/00 ,  B41J2/14129 ,  B41J2/14137 ,  B41J2202/13 ,  B81B2201/058 ,  B81B2207/015 ,  G01L9/0042 ,  G01L9/0098 ,  G01P15/0802 ,  G01P2015/0828

摘要： A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region.

摘要翻译： 一种方法包括与衬底中的第二氧化物区域同时生长第一氧化物区域并形成到第一氧化物区域的入口路径，入口路径暴露第一氧化物区域的第一表面。 该方法还包括去除第一氧化物区域以形成室，形成与第二氧化物区域相邻的第一MOS晶体管，以及通过第二氧化物区域形成与第一MOS晶体管分离的第二MOS晶体管。

公开(公告)号：US07514714B2

公开(公告)日：2009-04-07

申请号：US11355937

申请日：2006-02-16

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： H01L27/108 ,  H01L29/04 ,  H01L29/12 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/78624 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/7824

摘要： A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N− regions), and the second doped region could represent a p-type region (such as a P− region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.

摘要翻译： 薄膜功率晶体管包括在衬底上的多个第一掺杂区域和形成主体的第二掺杂区域。 身体的至少一部分设置在多个第一掺杂区域之间。 薄膜功率晶体管还包括在衬底上的栅极。 薄膜功率晶体管还包括介电层，其至少一部分设置在（i）栅极和（ii）第一和第二掺杂区域之间。 此外，薄膜功率晶体管包括接触多个第一掺杂区域的多个触点，其中多个第一掺杂区域形成薄膜功率晶体管的源极和漏极。 第一掺杂区域可以表示n型区域（例如N区域），并且第二掺杂区域可以表示p型区域（例如P-区域）。 第一掺杂区域也可以表示p型区域，第二掺杂区域可以表示n型区域。

公开(公告)号：US07465660B2

公开(公告)日：2008-12-16

申请号：US10424800

申请日：2003-04-28

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： H01L21/44

CPC分类号： H01L21/28061 ,  H01L29/4933

摘要： A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

摘要翻译： 在集成电路内采用具有调整到硅化物和相邻层之间的界面处的表面状态的可变内部金属浓度的硅化物。 在靠近相邻层的界面附近使用更高的硅/金属（富硅）比例，以减少与下面的多晶硅或上覆氧化物的晶格失配，从而减少应力和分层的可能性。 在硅化物的内部区域内采用较低的硅/金属比，降低了电阻率。 可变硅/金属比例通过在硅化物沉积期间控制反应气体浓度或流速来实现。 因此可能形成较少的分层可能性或金属氧化的较薄的硅化物。

公开(公告)号：US20060067607A1

公开(公告)日：2006-03-30

申请号：US10955891

申请日：2004-09-30

申请人： Ming Fang ,  Larry Tullos ,  Hai Ding

发明人： Ming Fang ,  Larry Tullos ,  Hai Ding

IPC分类号： G02B6/12

CPC分类号： G02B6/4204 ,  G02B6/4214

摘要： Connection between optical fibers and optical components within a semiconductor substrate. A lens is created at the front of a semiconductor substrate. A tapered hole is created in the back of the substrate exposing part or all of the surface of the lens. An optical component is formed or affixed at the front surface of the substrate. A volume of transparent adhesive is placed in the hole, followed by an optical fiber, which is thus coupled to the surface of the lens. A light guide is created on the front of the substrate overlying the lens to direct optical signals between the optical fiber inserted in the tapered hole and the optical component on the surface of the substrate.

摘要翻译： 半导体衬底内的光纤和光学部件之间的连接。 在半导体基板的前面形成透镜。 在基板的背面产生露出透镜的一部分或全部表面的锥形孔。 在基板的前表面上形成或固定光学部件。 将一定体积的透明粘合剂放置在孔中，随后是光纤，其由此耦合到透镜的表面。 在衬底的前面形成一个导光体，该导光体覆盖在透镜上，以将插入锥形孔中的光纤与基片表面上的光学部件之间的光信号引导。

公开(公告)号：US07389013B2

公开(公告)日：2008-06-17

申请号：US10955891

申请日：2004-09-30

申请人： Ming Fang ,  Larry R. Tullos ,  Hai Ding

发明人： Ming Fang ,  Larry R. Tullos ,  Hai Ding

IPC分类号： G02B6/12 ,  G02B6/124 ,  G02B6/00

CPC分类号： G02B6/4204 ,  G02B6/4214

摘要： Connection between optical fibers and optical components within a semiconductor substrate. A lens is created at the front of a semiconductor substrate. A tapered hole is created in the back of the substrate exposing part or all of the surface of the lens. An optical component is formed or affixed at the front surface of the substrate. A volume of transparent adhesive is placed in the hole, followed by an optical fiber, which is thus coupled to the surface of the lens. A light guide is created on the front of the substrate overlying the lens to direct optical signals between the optical fiber inserted in the tapered hole and the optical component on the surface of the substrate.

摘要翻译： 半导体衬底内的光纤和光学部件之间的连接。 在半导体基板的前面形成透镜。 在基板的背面产生露出透镜的一部分或全部表面的锥形孔。 在基板的前表面上形成或固定光学部件。 将一定体积的透明粘合剂放置在孔中，随后是光纤，其由此耦合到透镜的表面。 在衬底的前面形成一个导光体，该导光体覆盖在透镜上，以将插入锥形孔中的光纤与基片表面上的光学部件之间的光信号引导。