公开(公告)号：US10546947B2

公开(公告)日：2020-01-28

申请号：US16110330

申请日：2018-08-23

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

公开(公告)号：US20190252395A1

公开(公告)日：2019-08-15

申请号：US15983461

申请日：2018-05-18

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

IPC: H01L27/11521 ,  H01L21/225 ,  H01L21/266 ,  H01L29/66 ,  H01L29/08 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/11524 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7884

Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

公开(公告)号：US20190206881A1

公开(公告)日：2019-07-04

申请号：US15921858

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L27/11517 ,  H01L27/105

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

公开(公告)号：US20180233371A1

公开(公告)日：2018-08-16

申请号：US15887088

申请日：2018-02-02

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Mel Hymas

IPC: H01L21/28 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/423

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.