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    Method and apparatus for communication
    12.
    发明授权
    Method and apparatus for communication 有权

    公开(公告)号：US11296821B2

    公开(公告)日：2022-04-05

    申请号：US16806921

    申请日：2020-03-02

    Applicant: MEDIATEK INC.

    Inventor： Chong-You Lee ,  Cheng-Yi Hsu ,  Maoching Chiu ,  Timothy Perrin Fisher-Jeffes ,  Ju-Ya Chen ,  Yen Shuo Chang ,  Wei Jen Chen

    IPC: H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  H04L1/18

    Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

    HARQ buffer size design for communication systems
    13.
    发明授权
    HARQ buffer size design for communication systems 有权

    公开(公告)号：US11005602B2

    公开(公告)日：2021-05-11

    申请号：US16149085

    申请日：2018-10-01

    Applicant: MediaTek Inc.

    Inventor： Wei-De Wu ,  Timothy Perrin Fisher-Jeffes ,  Yen-Shuo Chang ,  Chia-Wei Tai ,  Hsien-Kai Hsin ,  Pei-Kai Liao

    IPC: H04L1/18 ,  H04L1/00

    Abstract: Techniques and examples of hybrid automatic repeat request (HARQ) buffer size design for communication systems are described. A user equipment (UE) communicates with a serving cell of a wireless network using a HARQ mechanism, with the communicating involving: (a) determining, by the processor, a respective size of each buffer of a plurality of buffers corresponding to a plurality of HARQ processes on a per-HARQ process basis; and (b) storing, by the processor, respective information in each buffer of the plurality of buffers for a corresponding HARQ process among the plurality of HARQ processes.

    Location of interleaver with LDPC code
    14.
    发明授权
    Location of interleaver with LDPC code 有权

    公开(公告)号：US10958290B2

    公开(公告)日：2021-03-23

    申请号：US16543783

    申请日：2019-08-19

    Applicant: MediaTek Inc.

    Inventor： Wei-Jen Chen ,  Ju-Ya Chen ,  Yen-Shuo Chang ,  Timothy Perrin Fisher-Jeffes ,  Mao-Ching Chiu ,  Cheng-Yi Hsu ,  Chong-You Lee

    IPC: H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H03M13/11

    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

    METHOD AND APPARATUS FOR ERROR CORRECTION CODING IN COMMUNICATION
    16.
    发明申请
    METHOD AND APPARATUS FOR ERROR CORRECTION CODING IN COMMUNICATION 审中-公开

    公开(公告)号：US20180278267A1

    公开(公告)日：2018-09-27

    申请号：US15917260

    申请日：2018-03-09

    Applicant: MEDIATEK INC.

    Inventor： Chong-You LEE ,  Timothy Perrin Fisher-Jeffes ,  Maoching Chiu ,  Wei Jen Chen ,  Cheng-Yi Hsu ,  Ju-Ya Chen ,  Yen Shuo Chang

    IPC: H03M13/11 ,  H03M13/15

    CPC classification number: H03M13/116 ,  H03M13/118 ,  H03M13/15 ,  H03M13/255 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6306 ,  H03M13/6516

    Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.

    Location Of Interleaver With LDPC Code
    17.
    发明申请
    Location Of Interleaver With LDPC Code 审中-公开

    公开(公告)号：US20180212626A1

    公开(公告)日：2018-07-26

    申请号：US15878350

    申请日：2018-01-23

    Applicant: MediaTek Inc.

    Inventor： Wei-Jen Chen ,  Ju-Ya Chen ,  Yen-Shuo Chang ,  Timothy Perrin Fisher-Jeffes ,  Mao-Ching Chiu ,  Cheng-Yi Hsu ,  Chong-You Lee

    IPC: H03M13/27 ,  H03M13/11 ,  H03M13/29 ,  H03M13/00

    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

    Method and apparatus for error correction coding in communication
    19.
    发明授权
    Method and apparatus for error correction coding in communication 有权

    公开(公告)号：US10608665B2

    公开(公告)日：2020-03-31

    申请号：US15917260

    申请日：2018-03-09

    Applicant: MEDIATEK INC.

    Inventor： Chong-You Lee ,  Timothy Perrin Fisher-Jeffes ,  Maoching Chiu ,  Wei Jen Chen ,  Cheng-Yi Hsu ,  Ju-Ya Chen ,  Yen Shuo Chang

    IPC: H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/25

    Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.

    Shift-coefficient table design of QC-LDPC code for larger code block sizes in mobile communications
    20.
    发明授权
    Shift-coefficient table design of QC-LDPC code for larger code block sizes in mobile communications 有权

    公开(公告)号：US10484011B2

    公开(公告)日：2019-11-19

    申请号：US16021015

    申请日：2018-06-28

    Applicant: MediaTek Inc.

    Inventor： Timothy Perrin Fisher-Jeffes ,  Chong-You Lee ,  Mao-Ching Chiu ,  Wei-Jen Chen ,  Ju-Ya Chen

    IPC: H03M13/11 ,  H03M13/03 ,  H03M13/00 ,  H04L1/00

    Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

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