公开(公告)号：US20230216571A1

公开(公告)日：2023-07-06

申请号：US18147732

申请日：2022-12-29

Applicant: MEDIATEK Inc.

Inventor： Da-Chun HSING ,  Wei-Yao CHEN ,  Nien-En WU ,  Chih-Wei CHEN ,  Yabo LI ,  Jiaxian PAN ,  Chong-You LEE ,  Wei-Jen CHEN ,  Chih-Yuan LIN ,  Jianwei ZHANG

IPC: H04B7/06

CPC classification number: H04B7/0691 ,  H04B7/0608

Abstract: The invention provides a method for antenna selectin of a user equipment (UE). The UE may comprise a plurality of antennas. The method may comprise calculating one or more quality evaluations respectively associated with one or more first antenna subsets, and selecting one of the one or more first antenna subsets according to the one or more quality evaluations. Each antenna subset may include one or more of the plurality of antennas. Each quality evaluation may be calculated under a condition that the antenna(s) included in the associated antenna subset is (are) used to communicate.

公开(公告)号：US20180323801A1

公开(公告)日：2018-11-08

申请号：US15971350

申请日：2018-05-04

Applicant: Mediatek Inc.

Inventor： Cheng-Yi HSU ,  Chong-You LEE ,  Wei Jen CHEN ,  Maoching CHIU ,  Timothy Perrin FISHER-JEFFES ,  Ju-Ya CHEN ,  Yen Shuo CHANG

IPC: H03M13/11 ,  H04L1/00

CPC classification number: H03M13/1162 ,  H04L1/0057 ,  H04L1/0071

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

公开(公告)号：US20180227077A1

公开(公告)日：2018-08-09

申请号：US15888733

申请日：2018-02-05

Applicant: MEDIATEK INC.

Inventor： Chong-You LEE ,  Cheng-Yi Hsu ,  Maoching Chiu ,  Timothy Perrin Fisher-Jeffes ,  Ju-Ya Chen ,  Yen Shuo Chang ,  Wei Jen Chen

IPC: H04L1/00 ,  H03M13/00 ,  H03M13/11

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

公开(公告)号：US20180278267A1

公开(公告)日：2018-09-27

申请号：US15917260

申请日：2018-03-09

Applicant: MEDIATEK INC.

Inventor： Chong-You LEE ,  Timothy Perrin Fisher-Jeffes ,  Maoching Chiu ,  Wei Jen Chen ,  Cheng-Yi Hsu ,  Ju-Ya Chen ,  Yen Shuo Chang

IPC: H03M13/11 ,  H03M13/15

CPC classification number: H03M13/116 ,  H03M13/118 ,  H03M13/15 ,  H03M13/255 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6306 ,  H03M13/6516

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.