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    QC-LDPC coding methods and apparatus
    13.
    发明授权
    QC-LDPC coding methods and apparatus 有权

    公开(公告)号：US10164659B2

    公开(公告)日：2018-12-25

    申请号：US15594239

    申请日：2017-05-12

    Applicant: MediaTek Inc.

    Inventor： Mao-Ching Chiu ,  Chong-You Lee ,  Cheng-Yi Hsu ,  Timothy Perrin Fisher-Jeffes ,  Yen-Shuo Chang ,  Wei-Jen Chen ,  Ju-Ya Chen

    IPC: H03M13/11 ,  H04L1/00 ,  H03M13/00 ,  H04L1/18

    Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

    NR LDPC With Interleaver
    14.
    发明申请
    NR LDPC With Interleaver 审中-公开

    公开(公告)号：US20180131392A1

    公开(公告)日：2018-05-10

    申请号：US15802265

    申请日：2017-11-02

    Applicant: MediaTek Inc.

    Inventor： Timothy Perrin Fisher-Jeffes ,  Wei-Jen Chen ,  Ju-Ya Chen ,  Mao-Ching Chiu ,  Yen-Shuo Chang ,  Cheng-Yi Hsu

    IPC: H03M13/25 ,  H03M13/27 ,  H04L1/00

    CPC classification number: H03M13/255 ,  H03M13/116 ,  H03M13/27 ,  H03M13/2742 ,  H03M13/6306 ,  H04L1/0041 ,  H04L1/0071

    Abstract: Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireless network. In encoding the data, the processor encodes the data with a low-density parity-check (LDPC) code to provide LDPC-coded data. Moreover, the processor processes the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data. The FEC robustness enhancement function includes an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

    Combined Coding Design For Efficient Codeblock Extension
    15.
    发明申请
    Combined Coding Design For Efficient Codeblock Extension 审中-公开

    公开(公告)号：US20180076923A1

    公开(公告)日：2018-03-15

    申请号：US15701431

    申请日：2017-09-11

    Applicant: MediaTek Inc.

    Inventor： Wei-De Wu ,  Mao-Ching Chiu

    IPC: H04L1/00 ,  H03M13/29 ,  H03M13/39

    Abstract: Concepts and examples pertaining to combined coding design for efficient codeblock extension are described. A processor of a communication apparatus may combine channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme. The processor may also code second codeblocks of a larger size using the second coding scheme.

    Method and apparatus for interference cancellation by a user equipment
    16.
    发明授权
    Method and apparatus for interference cancellation by a user equipment 有权
    用户设备干扰消除的方法和装置

    公开(公告)号：US09590667B1

    公开(公告)日：2017-03-07

    申请号：US14854067

    申请日：2015-09-15

    Applicant: MEDIATEK Inc.

    Inventor： Cheng-Yi Hsu ,  Mao-Ching Chiu ,  Wei-Nan Sun

    IPC: H04B7/02 ,  H04B1/04 ,  H04B7/04

    CPC classification number: H04B1/0475 ,  H04B7/0452 ,  H04L25/03891 ,  H04L27/0012

    Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

    Abstract translation: 用于干扰消除的装置包括：用于至少接收干扰信号和期望信号的前端处理电路; 内部处理电路，用于信道/噪声估计并用于抑制干扰信号; 以及MIMO（多输入多输出）处理电路，用于基于所抑制的干扰信号盲目地检测干扰信号的干扰参数，并且从所述期望信号共同抵消干扰信号，并基于 检测到的干扰参数和来自内部处理电路的信道/噪声估计。

    Bit Selection For Polar Coding Incremental-Redundancy HARQ
    20.
    发明申请
    Bit Selection For Polar Coding Incremental-Redundancy HARQ 有权

    公开(公告)号：US20220014211A1

    公开(公告)日：2022-01-13

    申请号：US17343618

    申请日：2021-06-09

    Applicant: MediaTek Inc.

    Inventor： Tun-Ping Huang ,  Mao-Ching Chiu ,  Wei-De Wu ,  Chia-Wei Tai ,  Tien-Yu Lin

    IPC: H03M13/09 ,  H03M13/13 ,  H04L1/18 ,  H04L1/00

    Abstract: Examples pertaining to bit selection for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) generates a re-transmission polar code block (CB) in a polar incremental redundancy HARQ (IR-HARQ) procedure. The apparatus then transmits the re-transmission polar CB as a re-transmission of an initial transmission of an initial polar code carrying a plurality of information bits. In generating the re-transmission polar CB, the apparatus selects one or more re-transmission information bits from the plurality of information bits.

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