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公开(公告)号：US20160187488A1
公开(公告)日：2016-06-30
申请号：US14585203
申请日：2014-12-30
Applicant: MEDIATEK INC.
Inventor： Chia-Yen Chong , Chih-Wei Chen , Chin-Tang Weng , Mu-Han Tsai
IPC: G01S19/25
Abstract: A satellite-based positioning method includes: obtaining predicted satellite data for at least one satellite vehicles (SVs) in a global navigation satellite system (GNSS); obtaining reference satellite data for the at least one SV; calculating satellite prediction error data for each of the at least one SV according to the predicted satellite data and the reference satellite data; and utilizing a processing unit to calculate a parameter for each of the at least one SV based on the satellite prediction error data. An associated satellite-based positioning apparatus is also provided.
Abstract translation: 基于卫星的定位方法包括：获取全球导航卫星系统（GNSS）中的至少一个卫星车辆（SV）的预测卫星数据; 获取所述至少一个SV的参考卫星数据; 根据预测的卫星数据和参考卫星数据计算至少一个SV中的每一个的卫星预测误差数据; 以及利用处理单元基于所述卫星预测误差数据来计算所述至少一个SV中的每一个的参数。 还提供了一种相关联的基于卫星的定位装置。
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公开(公告)号：US12184377B2
公开(公告)日：2024-12-31
申请号：US18147732
申请日：2022-12-29
Applicant: MEDIATEK Inc.
Inventor： Da-Chun Hsing , Wei-Yao Chen , Nien-En Wu , Chih-Wei Chen , Yabo Li , Jiaxian Pan , Chong-You Lee , Wei-Jen Chen , Chih-Yuan Lin , Jianwei Zhang
IPC: H04B7/0413 , H04B7/06
Abstract: The invention provides a method for antenna selectin of a user equipment (UE). The UE may comprise a plurality of antennas. The method may comprise calculating one or more quality evaluations respectively associated with one or more first antenna subsets, and selecting one of the one or more first antenna subsets according to the one or more quality evaluations. Each antenna subset may include one or more of the plurality of antennas. Each quality evaluation may be calculated under a condition that the antenna(s) included in the associated antenna subset is (are) used to communicate.
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公开(公告)号：US11983848B2
公开(公告)日：2024-05-14
申请号：US18151104
申请日：2023-01-06
Applicant: MEDIATEK INC.
Inventor： Cheng-Lung Jen , Pei-Kuei Tsung , Chih-Wei Chen , Yao-Sheng Wang , Shih-Che Chen , Yu-Sheng Lin , Chih-Wen Goo , Shih-Chin Lin , Tsung-Shian Huang , Ying-Chieh Chen
CPC classification number: G06T5/002 , G06T3/0093 , G06T3/4053 , G06T5/50 , G06T7/254 , G06T2207/20084 , G06T2207/20224
Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
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14.发明公开公开(公告)号：US20230401420A1
公开(公告)日：2023-12-14
申请号：US17838240
申请日：2022-06-12
Applicant: MediaTek Inc.
Inventor： Chih-Wen Goo , Pei-Kuei Tsung , Chih-Wei Chen , Mingen Shih , Shu-Hsin Chang , Po-Hua Huang , Ping-Yuan Tsai , Shih-Wei Hsieh , You Yu Nian
CPC classification number: G06N3/04 , G06F9/3001
Abstract: A system receives a neural network model that includes asymmetric operations. Each asymmetric operation includes one or more fixed-point operands that are asymmetrically-quantized from corresponding floating-point operands. The system compiles a given asymmetric operation of the neural network model into a symmetric operation that includes a combined bias value. A compiler computes the combined bias value is a constant by merging at least zero points of input and output of the given asymmetric operation. The system then generates a symmetric neural network model including the symmetric operation for inference hardware to execute in fixed-point arithmetic.
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公开(公告)号：US11836893B2
公开(公告)日：2023-12-05
申请号：US17167356
申请日：2021-02-04
Applicant: MediaTek Inc.
Inventor： Cheng Lung Jen , Pei-Kuei Tsung , Yao-Sheng Wang , Chih-Wei Chen , Chih-Wen Goo , Yu-Cheng Tseng , Ming-En Shih , Kuo-Chiang Lo
IPC: G06T3/40 , G06N3/04 , H04L65/75 , G06F18/214 , G06V10/764 , G06V10/774 , G06V20/40
CPC classification number: G06T3/4053 , G06F18/214 , G06N3/04 , G06T3/4046 , G06T3/4076 , G06V10/764 , G06V10/774 , G06V20/41 , H04L65/75
Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.
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Patent Agency Ranking
公开(公告)号：US11004232B2
公开(公告)日：2021-05-11
申请号：US16789376
申请日：2020-02-12
Applicant: MEDIATEK INC.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Shao-Yi Wang , Hung-Jen Chen , Kuan-Yu Chen , Cheng-Lung Jen
Abstract: An object detection apparatus includes a boundary box decision circuit and a processing circuit. The boundary box decision circuit receives lens configuration information of a lens, and refers to the lens configuration information to determine a bounding box distribution of bounding boxes that are assigned to different detection distances with respect to the lens for detection of a target object. The processing circuit receives a captured image that is derived from an output of an image capture device using the lens, and performs object detection upon the captured image according to the bounding box distribution of the bounding boxes.
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公开(公告)号：US12062151B2
公开(公告)日：2024-08-13
申请号：US17118162
申请日：2020-12-10
Applicant: MediaTek Inc.
Inventor： Ming-En Shih , Ping-Yuan Tsai , Yu-Cheng Tseng , Kuo-Chen Huang , Kuo-Chiang Lo , Hsin-Min Peng , Chun Hsien Wu , Pei-Kuei Tsung , Tung-Chien Chen , Yao-Sheng Wang , Cheng Lung Jen , Chih-Wei Chen , Chih-Wen Goo , Yu-Sheng Lin , Tsu Jui Hsu
IPC: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/00 , G09G5/391 , H01L21/033 , H04N9/31
CPC classification number: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/0002 , G09G5/391 , H01L21/0338 , H04N9/3188 , G06T2207/20081 , G06T2207/20084 , G06T2207/30168
Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
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公开(公告)号：US20230334619A1
公开(公告)日：2023-10-19
申请号：US17722711
申请日：2022-04-18
Applicant: MediaTek Inc.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Yao-Sheng Wang , Chun Chen Lin , Chia-Ching Lin , Hsiao-Chien Chiu
CPC classification number: G06T3/40 , G06T7/194 , H04N5/23296 , G06T7/571
Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.
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公开(公告)号：US20210334586A1
公开(公告)日：2021-10-28
申请号：US17191296
申请日：2021-03-03
Applicant: MediaTek Inc.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Chia-Da Lee , Yao-Sheng Wang , Hsiao-Chien Chiu , Cheng Lung Jen , Yu-Cheng Tseng , Kuo-Chiang Lo , Yu Chieh Lan
IPC: G06K9/62 , G06T5/00 , G06F3/0482 , G06F3/0484 , G06F16/58 , G06F16/51 , G06N20/00
Abstract: An image processing circuit stores a training database and models in memory. The image processing circuit includes an attribute identification engine to identify an attribute from an input image according to a model stored in the memory. By enhancing the input image based on the identified attribute, a picture quality (PQ) engine in the image processing circuit generates an output image for display. The image processing circuit further includes a data collection module to generate a labeled image based on the input image labeled with the identified attribute, and to add the labeled image to the training database. A training engine in the image processing circuit then re-trains the model using the training database.
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公开(公告)号：US20210287340A1
公开(公告)日：2021-09-16
申请号：US17167356
申请日：2021-02-04
Applicant: MediaTek Inc.
Inventor： Cheng Lung Jen , Pei-Kuei Tsung , Yao-Sheng Wang , Chih-Wei Chen , Chih-Wen Goo , Yu-Cheng Tseng , Ming-En Shih , Kuo-Chiang Lo
Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.
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