Abstract:
A technique, as well as select implementations thereof, pertaining to dynamic adjustment of speed of memory is described. The technique may involve obtaining information indicative of memory transactions associated with a memory device from an external memory interface coupled to the memory device. The technique may also involve determining a runtime bandwidth of the memory device according to the memory transactions. The technique may further involve comparing the runtime bandwidth of the memory device to at least one threshold bandwidth. The technique may additionally involve adjusting the speed of the memory device according to a result of the comparing.
Abstract:
A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
Abstract:
A multi-processor system performs thermal-aware task scheduling and task migration. Based on temperature measurements, the system determines one or more thermal conditions of each processor. The thermal conditions include a present temperature, a historical temperature, a predicted temperature, and thermal headroom of the processor. A scheduler identifies a target processor among the processors based on, at least in part, the one or more thermal conditions of each processor, and assigns a task to be executed by the target processor. For task migration, the system detects that a source processor satisfies a task migration criterion by comparing one or more of the thermal conditions of the source processor with corresponding thresholds. The scheduler identifies a target processor based on, at least in part, one or more of the thermal conditions of each processor, and migrates a task from the source processor to the target processor for execution.
Abstract:
A method and an apparatus for performing task-level cache management in an electronic device are provided. The method may be applied to a processing circuit of the electronic device, and may include: before a task of a plurality of tasks runs on a processor core, performing at least one checking operation on the task to generate at least one checking result, wherein the at least one checking result indicates whether the task is a risky task with risk of evicting cached data of an urgent task from a cache, and the cache is dedicated to a set of processor cores including the processor core; and according to the at least one checking result, determining whether to temporarily limit cache access permission of the processor core during a time period in which the task runs on the processor core, for preventing cache eviction of the cache due to the task.
Abstract:
Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy. The user-defined CPU hot-plug policy includes conservative policy, aggressive policy, and hot-plug-balanced policy. The user-defined task-migration policy includes performance policy, and task-migration-balanced policy.
Abstract:
A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.
Abstract:
Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.
Abstract:
An efficient, on-demand, content-based memory sharing method is performed by a system. The method begins when an event is detected. The system predicts a merge gain based on a current number of candidate pages in the memory, a current number of merged pages, and a merge ratio which represents a merged-to-candidate page ratio. In response to a determination that the merge gain is greater than a threshold, the system performs a scan and merge operation to merge a set of the candidate pages, which have a same content and have not been merged, into a single page having the same content.
Abstract:
A task scheduling method is applied to a heterogeneous multi-core processor system. The heterogeneous multi-core processor system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.
Abstract:
A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.